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publication number s29glxxxm revision a amendment 0 issue date january 29, 2004 preliminary s29glxxxm mirrorbit tm flash family s29gl256m, s29gl128m, s29gl064m, s29gl032m 256 megabit, 128 megabit, 64 megabit, and 32megabit, 3.0 volt-only page mode flash memory featuring 0.23 um mirrorbit process technology datasheet distinctive characteristics architectural advantages ? single power supply operation ? 3 volt read, erase, and program operations ? manufactured on 0.23 um mirrorbit process technology ? secsi ? (secured silicon) sector region ? 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random electronic serial number, accessible through a command sequence ? may be programmed and locked at the factory or by the customer ? flexible sector architecture ? 256mb: 512 32 kword (64 kbyte) sectors ? 128mb: 256 32 kword (64 kbyte) sectors ? 64mb (uniform sector models): 128 32 kword (64 kbyte) sectors or 128 32 kword sectors ? 64mb (boot sector models): 127 32kword (64 kbyte) sectors + 8 4kword (8kbyte) boot sectors ? 32mb (uniform sector models): 64 32 kwords (64 kbytes) sectors or 64 32 kword sectors ? 32mb (boot sector models): 63 32 kword (64 kbyte) sectors + 8 4 kword (8 kbyte) boot sectors ? compatibility with jedec standards ? provides pinout and software compatibility for single- power supply flash, and superior inadvertent write protection ? 100,000 erase cycles per sector typical ? 20-year data retention typical performance characteristics ? high performance ? 90 ns access time (128mb, 64mb, 32mb), 100 ns access time (256mb) ? 4-word/8-byte page read buffer ? 16-word/32-byte write buffer ? 25 ns page read times (128mb, 64mb, 32mb) ? 30 ns page read times (256mb) ? 16-word/32-byte write buffer reduces overall programming time for multiple-word updates ? low power consumption (typical values at 3.0 v, 5 mhz) ? 15 ma typical active read current ? 50 ma typical erase/program current ? 1 a typical standby mode current ? package options (specific package options vary by density) ? 40-pin tsop/rtsop ? 48-pin tsop/rtsop ? 56-pin tsop/rtsop ? 64-ball fortified bga ? 48-ball fine-pitch bga ? 63-ball fine-pitch bga ? 80-ball fine-pitch bga software & hardware features ? software features ? program suspend & resume: read other sectors before programming operation is completed ? erase suspend & resume: read/program other sectors before an erase operation is completed ? data# polling & toggle bits provide status ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? hardware features ? sector group protection: hardware-level method of preventing write operations within a sector group ? temporary sector unprotect: v id -level m ethod of charging code in locked sectors ? wp#/acc input accelerates programming time (when high voltage is applied) for greater throughput during system production. protects first or last sector regardless of sector protection settings ? hardware reset input (reset#) resets device ? ready/busy# output (ry/by#) detects program or erase cycle completion
2 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary general description the s29gl256/128/064/032m family of devices are 3.0 v single power flash memory manufactured using 0.23 um mirrorbit technology. the s29gl256m is a 256 mbit, organized as 16,777,216 words or 33,554,432 bytes. the s29gl128m is a 128 mbit, organized as 8,388,608 words or 16,777,216 bytes. the s29gl064m is a 64 mbit, organized as 4,194,304 words or 8,388,608 bytes. the s29gl032m is a 32 mbit, organized as 2,097,152 words or 4,194,304 bytes. de- pending on the model number, the devices have an 8-bit wide data bus only, 16- bit wide data bus only, or a 16-bit wide data bus that can also function as an 8- bit wide data bus by using the byte# input. the devices can be programmed ei- ther in the host system or in standard eprom programmers. access times as fast as 90 ns (s29gl128m, s29gl064m, s29gl032m) or 100 ns (s29gl256m) are available. note that each access time has a specific operating voltage range (v cc ) as specified in the product selector guide and the ordering information sections. package offerings include 40-pin tsop, 48-pin tsop, 56-pin tsop, 48-ball fine-pitch bga, 63-ball fine-pitch bga, 80-ball fine-pitch bga and 64-ball fortified bga, depending on model number. each device has separate chip enable (ce#), write enable (we#) and output enable (oe#) controls. each device requires only a single 3.0 volt power supply for both read and write functions. in addition to a v cc input, a high-voltage accelerated program (acc) feature provides shorter programmin g times through increased current on the wp#/acc or acc input, depending on model number. this feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. the device is entirely command set compatible with the jedec single-power- supply flash standard . commands are written to the device using standard mi- croprocessor write timing. write cycles also internally latch addresses and data needed for the programming and erase operations. the sector erase architecture allows memory sectors to be erased and repro- grammed without affecting the data contents of other sectors. the device is fully erased when shipped from the factory. device programming and erasure are initiated through command sequences. once a program or erase operation has begun, the host system need only poll the dq7 (data# polling) or dq6 (toggle) status bits or monitor the ready/busy# (ry/by#) output to determine whether the operation is complete. hardware data protection measures include a low v cc detector that automat- ically inhibits write operations during power transitions. the hardware sector protection feature disables both progra m and erase operations in any combina- tion of sectors of memory. this can be achieved in-system or via programming equipment. the erase suspend/erase resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. the program suspend/program resume fea- ture enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. the hardware reset# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the device,
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 3 preliminary enabling the host system to read bo ot-up firmware from the flash memory device. the device reduces power consumption in the standby mode when it detects specific voltage levels on ce# and reset#, or when addresses have been stable for a specified period of time. the write protect (wp#) feature protects the first or last sector by asserting a logic low on the wp#/acc pin or wp# pin, depending on model number. the protected sector will still be protected even during accelerated programming. the secsi ? (secured silicon) sector provides a 128-word/256-byte area for code or data that can be permanently protected. once this sector is protected, no further changes within the sector can occur. spansion mirrorbit flash technology combines years of flash memory manufac- turing experience to produce the highest levels of quality, reliability and cost effectiveness. the device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. the data is programmed using hot electron injection.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbittm flash family 4 table of contents product selector guide . . . . . . . . . . . . . . . . . . . . . .6 s29gl256m .............................................................................................................6 s29gl128m ..............................................................................................................6 s29gl064m .............................................................................................................6 s29gl032m .............................................................................................................6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 connection diagrams . . . . . . . . . . . . . . . . . . . . . . .8 special package handling instructions ...........................................................13 special package handling instructions .......................................................... 14 logic symbol-s29gl032m (model r0) ......................................................... 16 logic symbol-s29gl032m (models r1, r2) ................................................. 16 logic symbol-s29gl032m (models r3, r4) ................................................ 16 logic symbol-s29gl064m (model r0) .........................................................17 logic symbol-s29gl064m (models r1, r2) .................................................17 logic symbol-s29gl064m (models r3, r4) ................................................17 logic symbol-s29gl064m (model r5) ......................................................... 18 logic symbol-s29gl064m (model r6, r7) ................................................. 18 logic symbol-s29gl128m ................................................................................. 18 logic symbol-s29gl256m ................................................................................ 19 ordering information-s29gl032m . . . . . . . . . . . .20 s29gl032m standard products ..................................................................... 20 ordering information-s29gl064m . . . . . . . . . . . .22 s29gl064m standard products ..................................................................... 22 ordering information-s29gl128m . . . . . . . . . . . .24 s29gl128m standard products ...................................................................... 24 ordering information-s29gl256m . . . . . . . . . . . .25 s29gl256m standard products ......................................................................25 device bus operations . . . . . . . . . . . . . . . . . . . . . .26 table 1. device bus operations ........................................... 26 word/byte configuration ............................................................................... 26 requirements for reading array data ........................................................ 26 page mode read ..............................................................................................27 writing commands/command sequences .................................................27 write buffer .....................................................................................................27 accelerated program operation ...............................................................27 autoselect functions .................................................................................... 28 standby mode ...................................................................................................... 28 automatic sleep mode ..................................................................................... 28 reset#: hardware reset pin ........................................................................ 28 output disable mode ....................................................................................... 29 table 2. s29gl032m (model r0) sector address table ........... 30 table 3. s29gl032m (models r1, r2) sector address table .... 32 table 4. s29gl032m (model r3) top boot sector architecture 34 table 5. s29gl032m (model r4) bottom boot sector architecture 36 table 6. s29gl064m (model r0) sector address table ........... 38 table 7. s29gl064m (models r1, r2) sector address table .... 42 table 8. s29gl064m (model r3) top boot sector architecture 46 table 9. s29gl064m (model r4) bottom boot sector architecture 50 table 10. s29gl064m (model r5) sector address table ......... 53 table 11. s29gl064m (models r6, r7) sector address table .. 56 table 12. s29gl128m sector address table ......................... 60 table 13. s29gl256m sector address table ......................... 66 autoselect mode .................................................................................................77 table 14. autoselect codes, (high voltage method) .............. 78 sector group protection and unprotection ............................................. 78 table 15. s29gl032m (model r0) sector group protection/unpro - tection address table ........................................................ 79 table 16. s29gl032m (model r1) top boot sector protection .. 79 table 17. s29gl032m (model r2) bottom boot sector protection ............................................................... 80 table 18. s29gl032m (models r3, r4) sector group protection/un - protection address table .................................................... 81 table 19. s29gl065m (model r0) sector group protection/unpro - tection address table ........................................................ 82 table 20. s29gl064m (model r1) top boot sector protection .. 83 table 21. s29gl064m (model r2) bottom boot sector protection ............................................................... 84 table 22. s29gl064m (model r3, r4) sector group protection/un - protection address table .................................................... 85 table 23. s29gl064m (model r5) sector group protection/unpro - tection address table ........................................................ 86 table 24. s29gl064m (models r6, r7) sector group protection/un - protection address table .................................................... 87 table 25. s29gl128m sector group protection/unprotection address table .................................................................... 87 table 26. s29gl256m sector group protection/unprotection address table .................................................................... 89 temporary sector group unprotect .......................................................... 93 figure 1. temporary sector group unprotect operation .......... 93 figure 2. in-system sector group protect/unprotect algorithms............................................... 94 secsi (secured silicon) sector flash memory region ............................. 95 write protect (wp#) ....................................................................................... 96 hardware data protection ............................................................................. 96 low vcc write inhibit ............................................................................... 96 write pulse ?glitch? protection ............................................................... 97 logical inhibit ................................................................................................... 97 power-up write inhibit ............................................................................... 97 common flash memory interface (cfi) . . . . . . . 97 table 28. system interface string ........................................ 98 command definitions . . . . . . . . . . . . . . . . . . . . . 101 reading array data ...........................................................................................101 reset command .................................................................................................101 autoselect command sequence ..................................................................102 enter secsi sector/exit secsi sector command sequence ..................102 write buffer programming ........................................................................102 accelerated program ...................................................................................104 figure 3. write buffer programming operation..................... 105 program suspend/program resume command sequence ...................106 figure 4. program suspend/program resume ...................... 107 chip erase command sequence ..................................................................107 sector erase command sequence .............................................................. 108 figure 5. erase operation ................................................. 109 erase suspend/erase resume commands .................................................109 command definitions ........................................................................................ 111 table 31. command definitions (x16 mode, byte# = v ih ) .... 111 table 32. command definitions (x8 mode, byte# = v il )....... 112 write operation status ................................................................................... 113 dq7: data# polling ........................................................................................... 113 figure 6. data# polling algorithm ...................................... 114 ry/by#: ready/ busy# .......................................................................................114 dq6: toggle bit i ............................................................................................... 115 figure 7. toggle bit algorithm ........................................... 116 dq2: toggle bit ii ..............................................................................................116 reading toggle bits dq6/dq2 ..................................................................... 117 dq5: exceeded timing limits ........................................................................ 117 dq3: sector erase timer ................................................................................ 117
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbittm flash family 5 dq1: write-to-buffer abort .......................................................................... 118 table 33. write operation status ........................................118 figure 8. maximum negative overshoot waveform ............... 119 figure 9. maximum positive overshoot waveform ........................................................ 119 operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . 119 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . 120 test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 figure 10. test setup ....................................................... 121 table 34. test specifications ............................................. 121 key to switching waveforms . . . . . . . . . . . . . . . 121 figure 11. input waveforms and measurement levels ......................................................... 121 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . 122 read-only operations-s29gl256m only .................................................. 122 read-only operations-s29gl128m only ................................................... 122 read-only operations-s29gl064m only .................................................. 123 read-only operations-s29gl032m only .................................................. 123 figure 12. read operation timings ..................................... 124 figure 13. page read timings ............................................ 124 hardware reset (reset#) ............................................................................. 125 figure 14. reset timings ................................................... 125 erase and program operations-s29gl256m only .................................. 126 erase and program operations-s29gl128m only ................................... 127 erase and program operations-s29gl064m only .................................. 128 erase and program operations-s29gl032m only .................................. 129 figure 15. program operation timings ................................ 130 figure 16. accelerated program timing diagram .................. 130 figure 17. chip/sector erase operation timings ................... 131 figure 18. data# polling timings (during embedded algorithms).......................................... 132 figure 19. toggle bit timings (during embedded algorithms) 133 figure 20. dq2 vs. dq6 .................................................... 133 temporary sector unprotect ....................................................................... 134 figure 21. temporary sector group unprotect timing diagram 134 figure 22. sector group protect and unprotect timing diagram 135 alternate ce# controlled erase and program operations- s29gl256m ......................................................................................................... 136 alternate ce# controlled erase and program operations- s29gl128m .......................................................................................................... 137 alternate ce# controlled erase and program operations- s29gl064m .........................................................................................................138 alternate ce# controlled erase and program operations- s29gl032m ......................................................................................................... 139 figure 23. alternate ce# controlled write (erase/program) operation timings............................................................ 140 erase and programming performance . . . . . . . . 141 latchup characteristics . . . . . . . . . . . . . . . . . . . 141 tsop pin and bga package capacitance . . . . 142 for package types ta, tf, ba, bf, fa, ff (refer to ordering information pages): ..................................................142 for package types tb, tc, bb, bc (refer to ordering information pages): ..................................................142 physical dimensions . . . . . . . . . . . . . . . . . . . . . . .143
6 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary product selector guide s29gl256m s29gl128m s29gl064m s29gl032m part number s29gl256m speed option 10 11 max. access time (ns) 100 110 max. ce# access time (ns) 100 110 max. page access time (ns) 30 30 max. oe# access time (ns) 30 30 part number s29gl128m speed option 90 10 max. access time (ns) 90 100 max. ce# access time (ns) 90 100 max. page access time (ns) 25 30 max. oe# access time (ns) 25 30 part number s29gl064m speed option 90 10 11 max. access time (ns) 90 100 110 max. ce# access time (ns) 90 100 110 max. page access time (t pacc ) 25 30 30 max. oe# access time (ns) 25 30 30 part number s29gl032m speed option 90 100 11 max. access time (ns) 90 100 110 max. ce# access time (ns) 90 100 110 max. page access time (t pacc ) 25 30 30 max. oe# access time (ns) 25 30 30
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 7 preliminary block diagram input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# wp#/acc byte# ce# oe# stb stb dq15 ? dq0 (a-1) sector switches ry/by# reset# data latch y-gating cell matrix address latch a max **?a0 ** a max gl256m = a23, a max gl128m = a22, a max gl064m = a21 (a max gl064m-00 = a22), a max gl032m = a20 (a max gl032m-00 = a21)
8 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we# reset# acc ry/by# a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss a20 a19 a10 dq7 dq6 dq5 oe# v ss ce# a0 dq4 v cc v cc a21 dq3 dq2 dq1 1 16 2 3 4 5 6 7 8 17 18 19 20 9 10 11 12 13 14 15 40 25 39 38 37 36 35 34 33 32 31 30 29 28 27 26 24 23 22 21 a16 a5 a15 a14 a13 a12 a11 a9 a8 we# reset# acc ry/by# a18 a7 a6 a4 a3 a2 a1 a17 dq0 v ss a20 a19 a10 dq7 dq6 dq5 oe# v ss ce# a0 dq4 v cc v cc a21 dq3 dq2 dq1 40-pin standard tsop 40-pin reverse tsop
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 9 preliminary connection diagrams 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 v cc v ss dq15 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin standard tsop 1 16 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 9 10 11 12 13 14 15 48 33 47 46 45 44 43 42 41 40 39 38 37 36 35 34 25 32 31 30 29 28 27 26 a15 a18 a14 a13 a12 a11 a10 a9 a8 a21 a20 we# reset# acc wp# a19 a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 v cc v ss dq15 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 48-pin reverse tsop
10 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary connection diagrams 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc nc 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc 23 24 25 26 27 28 nc nc 34 33 32 31 30 29 nc v cc a15 a18 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a1 a17 a7 a6 a5 a4 a3 a2 a16 dq2 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq9 dq1 dq8 dq0 oe# v ss ce# a0 dq5 dq12 dq4 v cc dq11 dq3 dq10 56-pin standard tsop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 nc nc a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 nc nc a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 23 24 25 26 27 28 a4 a3 a2 a1 nc nc 34 33 32 31 30 29 oe# v ss ce# a0 nc v cc 56-pin reverse tsop
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 11 preliminary connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop and bga). the package and/or data integrity may be compromised if the package body is exposed to temperatures above 150c for prolonged periods of time. notes: 1. ball c5 is nc on s29gl032m. 2. ball b8 is nc on s29gl064m and s29gl032m. 3. ball c8 is nc on s29gl128m and s29gl032m. a2 c2 d2 e2 f2 g2 h2 a3 c3 d3 e3 f3 g3 h3 a4 c4 d4 e4 f4 g4 h4 a5 c5 d5 e5 f5 g5 h5 a6 c6 d6 e6 f6 g6 h6 a7 c7 d7 e7 f7 g7 h7 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 1 reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 a1 c1 d1 e1 f1 g1 h1 nc nc v io nc nc nc nc nc a8 c8 b2 b3 b4 b5 b6 b7 b1 b8 d8 e8 f8 g8 h8 nc nc nc v ss v cc a23 3 a22 2 nc 64-ball fortified bga top view, balls facing down
12 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, ssop, pdip, plcc). the pack age and/or data integrity may be com- promised if the package body is exposed to temperatures above 150c for prolonged periods of time. c2 d2 e2 f2 g2 h2 j2 k2 c3 d3 e3 f3 g3 h3 j3 k3 c4 d4 e4 f4 g4 h4 j4 k4 c5 d5 e5 f5 g5 h5 j5 k5 c6 d6 e6 f6 g6 h6 j6 k6 c7 d7 a7 b7 a8 b8 a1 b1 a2 e7 f7 g7 h7 j7 k7 l7 l8 m7 m8 l1 l2 m1 m2 nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc* nc nc nc nc dq15 v ss v cc a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 a21 reset# we# dq11 dq3 dq10 dq2 a20 a18 acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 * balls are shorted together via the substrate but not connected to the die. 63-ball fine-pitch bga top view, balls facing down
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 13 preliminary connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, ssop, pdip, plcc). the pack age and/or data integrity may be com- promised if the package body is exposed to temperatures above 150c for prolonged periods of time. a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 dq15/a-1 v ss byte# a16 a15 a14 a12 a13 dq13 dq6 dq14 dq7 a11 a10 a8 a9 v cc dq4 dq12 dq5 a19 nc reset# we# dq11 dq3 dq10 dq2 a20 a18 wp#/acc ry/by# dq9 dq1 dq8 dq0 a5 a6 a17 a7 oe# v ss ce# a0 a1 a2 a4 a3 48-ball fine-pitch bga top view, balls facing down
14 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary connection diagrams special package handling instructions special handling is required for flash memory products in molded packages (tsop, bga, ssop, pdip, plcc). the pack age and/or data integrity may be com- promised if the package body is exposed to temperatures above 150c for prolonged periods of time. e6 a 10 e5 e4 a 18 e3 a 6 e2 a 2 g4 dq 2 g3 dq 0 g2 a 0 h6 dq 14 h5 dq 12 h4 dq 10 h3 dq 8 h2 ce# f6 a 11 f3 a 5 f2 a 1 j6 dq 13 j5 v cc j4 dq 11 j3 dq 9 j2 oe# k6 dq 6 k5 dq 4 k4 dq 3 k3 dq 1 k2 v ss l7 nc l2 nc l1 nc l8 nc d6 a 8 d5 reset# d4 wp#/acc d3 a 17 d2 a 4 m7 nc m2 nc m1 nc m8 nc c6 a 9 c5 we# c4 ry/by# c3 a 7 c2 a 3 b7 nc b1 nc b8 nc a7 nc a2 nc a1 nc a8 nc f5 a 19 g5 dq 5 f4 a 20 g6 dq 7 e7 a 14 g7 a 16 h7 byte# f7 a 15 j7 dq 15 /a -1 k7 v ss d7 a 12 c7 a 13 e8 g8 h8 f8 j8 k8 v ss d8 c8 nc v cc nc e1 g1 h1 f1 j1 k1 v cc d1 c1 nc v cc nc nc nc nc v ss b2 nc nc nc nc nc a 21 80-ball fine-pitch bga top view, balls facing down
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 15 preliminary pin description a23?a0 = 24 address inputs a22?a0 = 23 address inputs a21?a0 = 22 address inputs a20?a0 = 21 address inputs dq7?dq0 = 8 data inputs/outputs dq14?dq0 = 15 data inputs/outputs dq15/a-1 = dq15 (data input/output, word mode), a-1 (lsb address input, byte mode) ce# = chip enable input oe# = output enable input we# = write enable input wp#/acc = hardware write protect input/programming acceleration input acc = acceleration input wp# = hardware write protect input reset# = hardware reset pin input ry/by# = ready/busy output byte# = selects 8-bit or 16-bit mode v cc = 3.0 volt-only single power supply (see product selector guide for speed options and voltage supply tolerances) v ss = device ground nc = pin not connected internally
16 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary logic symbol-s29gl032m (model r0) logic symbol-s29gl032m (models r1, r2) logic symbol-s29gl032m (models r3, r4) 22 8 dq7?dq0 a21?a0 ce# oe# we# reset# ry/by# acc 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# ry/by# wp#/acc byte# 21 16 or 8 dq15?dq0 (a-1) a20?a0 ce# oe# we# reset# ry/by# wp#/acc byte#
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 17 preliminary logic symbol-s29gl064m (model r0) logic symbol-s29gl064m (models r1, r2) logic symbol-s29gl064m (models r3, r4) 23 8 dq7?dq0 (a-1) a22?a0 ce# oe# we# reset# ry/by# acc 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# oe# we# reset# ry/by# wp#/acc byte# 22 16 or 8 dq15?dq0 (a-1) a21?a0 ce# we# reset# ry/by# wp#/acc byte# oe#
18 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary logic symbol-s29gl064m (model r5) logic symbol-s29gl064m (model r6, r7) logic symbol-s29gl128m 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# ry/by# acc 22 16 dq15?dq0 a21?a0 ce# oe# we# reset# acc wp# 23 16 or 8 dq15?dq0 (a-1) a22?a0 ce# oe# we# reset# ry/by# wp#/acc byte#
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 19 preliminary logic symbol-s29gl256m 24 16 or 8 dq15?dq0 (a-1) a23?a0 ce# oe# we# reset# ry/by# wp#/acc byte#
20 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ordering information-s29gl032m s29gl032m standard products standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: s29gl032m 10 t a i r1 2 packing type 2 = 7? tape and reel model number r0 = x8, v cc =3.0-3.6v, uniform sector device r1 = x8/x16, v cc =3.0-3.6v, uniform sector device, highest address sector protected when wp#/acc=v il r2 = x8/x16, v cc =3.0-3.6v, uniform sector device, lowest address sector protected when wp#/acc=v il r3 = x8/x16, v cc =3.0-3.6v, top boot sector device, top two address sectors protected r4 = x8/x16, v cc =3.0-3.6v, bottom boot sector device, bottom two address sectors protected temperature range i = industrial (?40 c to +85 c) package material set a = standard [for 48-pin tsops, cu lead frame] f = pb-free [for 48-pin tsops, cu lead frame] b = standard [for 48-pin tsops, alloy-42 lead frame] c = pb-free [for 48-pin tsops, alloy-42 lead frame] package type t = thin small outline package (tsop) standard pinout r = thin small outline package (tsop) reverse pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl032m 32 megabit page-mode flash memory manufactured using 0.23 um mirrorbit tm process technology, 3.0 volt-only read, program, and erase
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 21 preliminary note: 1. the package marking consits of characters 4-16 of the 17 character order number valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. note: 1. for availability of ordering numbers beginning with s29gl 032m90 and s29gl032m95. valid combinations for tsop package package s29gl032m10 s29gl032m11 ta i tfi r02 ts040 ta i tfi r12 r22 ts056 ta i tfi r32 r42 ts048 tbi tci fpt-48p-m19 valid combinations for bga package package s29gl032m10 s29gl032m11 bai bfi r02 fbc048 fai ffi r12 r22 laa064 bai bfi r32 r42 fbc048 fai ffi laa064 bbi bci bga-48p-m20
22 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ordering information-s29gl064m s29gl064m standard products standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: s29gl064m 90 t a i r1 2 package type 2 = 7? tape and reel model number r0 = x8, v cc =3.0-3.6v, uniform sector device r1 = x8/x16, v cc =3.0-3.6v, uniform sector device, highest address sector protected when wp#/acc=v il r2 = x8/x16, v cc =3.0-3.6v, uniform sector device, lowest address sector protected when wp#/acc=v il r3 = x8/x16, v cc =3.0-3.6v, top boot sector device, top two address sectors protected r4 = x8/x16, v cc =3.0-3.6v, bottom boot sector device, bottom two address sectors protected r5 = x16, v cc =3.0-3.6v, uniform sector device r6 = x16, v cc =2.7-3.6v, uniform sector device, highest address sector protected when wp#=v il r7 = x16, v cc =3.0-3.6v, uniform sector device, lowest address sector protected when wp#=v il r8 = x8/x16, v cc =3.0-3.6v, uniform sector device, highest address sector protected when wp#/acc=v il r9 = x8/x16, v cc =3.0-3.6v, uniform sector device, lowest address sector protected when wp#/acc=v il temperature range i = industrial (?40 c to +85 c) package material set a = standard [for 48-pin tsops, cu lead frame] f = pb-free [for 48-pin tsops, cu lead frame] b = standard [for 48-pin tsops, alloy-42 lead frame] c = pb-free [for 48-pin tsops, alloy-42 lead frame] package type t = thin small outline package (tsop) standard pinout r = thin small outline package (tsop) reverse pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl064m 64 megabit page-mode flash memory manufactured using 0.23 um mirrorbit tm process technology, 3.0 volt-only read, program, and erase
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 23 preliminary note: 1. the package marking consits of characters 4-16 of the 17 character order number valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid com- binations and to check on newly released combinations. valid combinations for tsop package package s29gl064m90 s29gl064m10 s29gl064m11 ta i tfi r02 r32 r42 r62 r72 ts040 ta i tfi r12 r22 ts056 tbi tci r12 r22 r62 r72 fpt-48p-m19 zbi zci r82 r92 fpt-56p-m01 valid combinations for bga package package s29gl064m90 s29gl064m10 s29gl064m11 bai bfi r02 r32 r42 r52 fbc048 fai ffi r12 r22 r32 r42 r52 laa064 bbi bci r12 r22 bga-80p-m01 bbi bci r52 bga-63p-m02
24 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ordering information-s29gl128m s29gl128m standard products standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: note: 1. the package marking consits of characters 4-16 of the 17 character order number valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29gl128m 90 t a i r1 2 package type 2 = 7? tape and reel model number r1 = x8/x16, v cc =3.0-3.6v, uniform sector device, highest address sector protected when wp#/acc=v il r2 = x8/x16, v cc =3.0-3.6v, uniform sector device, lowest address sector protected when wp#/acc=v il temperature range i = industrial (?40 c to +85 c) package material set a = standard [for tsops, cu lead frame] f = pb-free [for tsops, cu lead frame] b = standard [for tsops, alloy-42 lead frame] c = pb-free [for tsops, alloy-42 lead frame] package type t = thin small outline package (tsop) standard pinout r = thin small outline package (tsop) reverse pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl128m 128 megabit page-mode flash memory manufactured using 0.23 um mirrorbit tm process technology, 3.0 volt-only read, program, and erase valid combinations for tsop package package s29gl128m90 s29gl128m10 ta i tfi r12 r22 ts056 tbi tci fpt-56p-m01 valid combinations for bga package package s29gl128m90 s29gl0128m10 fai ffi r12 r22 laa064
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 25 preliminary ordering information-s29gl256m s29gl256m standard products standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of the following: note: 1. the package marking consits of characters 4-16 of the 17 character order number valid combinations valid combinations list configurations planned to be supported in volume for this device. consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. s29gl256m 10 t a i r1 2 package type 2 = 7? tape and reel model number r1 = x8/x16, v cc =3.0-3.6v, uniform sector device, highest address sector protected when wp#/acc=v il r2 = x8/x16, v cc =3.0-3.6v, uniform sector device, lowest address sector protected when wp#/acc=v il temperature range i = industrial (?40 c to +85 c) package material set a= standard f = pb-free package type t = thin small outline package (tsop) standard pinout r = thin small outline package (tsop) reverse pinout b = fine-pitch ball-grid array package f = fortified ball-grid array package speed option see product selector guide and valid combinations device number/description s29gl1256m 256 megabit page-mode flash memory manufactured using 0.23 um mirrorbit tm process technology, 3.0 volt-only read, program, and erase valid combinations for tsop package package s29gl256m10 s29gl256m11 ta i tfi r12 r22 ts056 valid combinations for bga package package s29gl256m10 s29gl256m11 fai ffi r12 r22 lac064
26 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary device bus operations this section describes the requirements and use of the device bus operations, which are initiated through the internal command register. the command register itself does not occupy any addressable memory location. the register is a latch used to store the commands, along with the address and data information needed to execute the command. the contents of the register serve as inputs to the internal state machine. the state mach ine outputs dictate the function of the device. table 1 lists the device bus operations, the inputs and control levels they require, and the resulting output. the fo llowing subsections describe each of these operations in further detail. ta b l e 1 . device bus operations legend: l = logic low = v il , h = logic high = v ih , v id = 11.5?12.5 v, v hh = 11.5?12.5v, x = don?t care, sa = sector address, a in = address in, d in = data in, d out = data out notes: 1. addresses are amax:a0 in word mode; a max :a-1 in byte mode. sector addresses are a max :a16 in both modes. 2. if wp# = v il , the first or last sector group remains protected. if wp# = v ih , the first or last sector will be protected or unprotected as determined by the method described in ?write protect (wp#)?. all sectors are unprotected when shipped from the factory (the secsi sector may be factory protected depending on version ordered.) 3. d in or d out as required by command sequence, data polling, or sector protect algorithm (see figure 2). word/byte configuration the byte# pin controls whether the device data i/o pins operate in the byte or word configuration. if the byte# pin is set at logic ?1?, the device is in word con- figuration, dq0?dq15 are active and controlled by ce# and oe#. if the byte# pin is set at logic ?0?, the device is in byte configuration, and only data i/o pins dq0?dq7 are active and controlled by ce# and oe#. the data i/ o pins dq8?dq14 are tri-stated, and the dq15 pin is used as an input for the lsb (a-1) address function. requirements for reading array data to read array data from the outputs, the system must drive the ce# and oe# pins to v il . ce# is the power control and selects the device. oe# is the output control and gates array data to the output pins. we# should remain at v ih . operation ce# oe# we# reset# wp# acc addresses (note 2) dq0? dq7 dq8?dq15 byte# = v ih byte# = v il read llh h x x a in d out d out dq8?dq14 = high-z, dq15 = a-1 write (program/erase) l h l h (note 2) x a in (note 3) (note 3) accelerated program l h l h (note 2) v hh a in (note 3) (note 3) standby v cc 0.3 v xx v cc 0.3 v x h x high-z high-z high-z output disable l h h h x x x high-z high-z high-z reset x x x l x x x high-z high-z high-z
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 27 preliminary the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory content occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. see ?reading array data? for more information. refer to the ac read-only op- erations table for timing specifications and the timing diagram. refer to the dc characteristics table for the active current specification on reading array data. page mode read the device is capable of fast page mode read and is compatible with the page mode mask rom read operation. this mode provides faster read access speed for random locations within a page. the page size of the device is 8 words/16 bytes. the appropriate page is selected by the higher address bits a(max)?a3. address bits a2?a0 in word mode (a2?a-1 in byte mode) determine the specific word within a page. this is an asynchronous operation; the microprocessor supplies the specific word location. the random or initial page access is equal to t acc or t ce and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t pacc . when ce# is deasserted and reasserted for a subsequent access, the access time is t acc or t ce . fast page mode accesses are obtained by keeping the ?read-page addresses? constant and changing the ?intra-read page? addresses. writing commands/command sequences to write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the system must drive we# and ce# to v il , and oe# to v ih . an erase operation can erase one sector, multiple sectors, or the entire device. table 2 indicates the address space that each sector occupies. refer to the dc characteristics table for the active current specification for the write mode. the ac characteristics section contains timing specification tables and timing diagrams for write operations. write buffer write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. see ?write buffer? for more information. accelerated program operation the device offers accelerated program operations through the acc function. this is one of two functions provided by the wp#/acc or acc pin, depending on model number. this function is primarily intended to allow faster manufacturing throughput at the factory. if the system asserts v hh on this pin, the device temporarily unprotects any pro- tected sector groups, and uses the higher voltage on the pin to reduce the time required for program operations. removing v hh from the wp#/acc or acc pin returns the device to normal operation. note that the wp#/acc or acc pin must
28 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary not be at v hh for operations other than accelerated programming, or device dam- age may result. wp# has an internal pullup; when unconnected, wp# is at v ih . autoselect functions if the system writes the autoselect comm and sequence, the device enters the au- toselect mode. the system can then read autoselect codes from the internal register (which is separate from the memory array) on dq7?dq0. standard read cycle timings apply in this mode. refer to the ?autoselect mode? section on page 77 and ?autoselect command sequence? section on page 102 sections for more information. standby mode when the system is not reading or writing to the device, it can place the device in the standby mode. in this mode, current consumption is greatly reduced, and the outputs are placed in the high im pedance state, independent of the oe# input. the device enters the cmos standby mode when the ce# and reset# pins are both held at v cc 0.3 v. (note that this is a more restricted voltage range than v ih .) if ce# and reset# are held at v ih , but not within v cc 0.3 v, the device will be in the standby mode, but the standby current will be greater. the device requires standard access time (t ce ) for read access when the device is in either of these standby modes, before it is ready to read data. if the device is deselected during eras ure or programming, the device draws ac- tive current until the operation is completed. refer to the ?dc characteristics? section on page 129 for the standby current specification. automatic sleep mode the automatic sleep mode minimizes flash device energy consumption. the de- vice automatically enables this mode when addresses remain stable for t acc + 30 ns. the automatic sleep mode is independent of the ce#, we#, and oe# con- trol signals. standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. refer to the ?dc characteristics? section on page 129 for the automatic sleep mode current specification. reset#: hardware reset pin the reset# pin provides a hardware method of resetting the device to reading array data. when the reset# pin is driven low for at least a period of t rp , the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset# pulse. the device also resets the internal state machine to reading array data. the op- eration that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. current is reduced for the duration of th e reset# pulse. when reset# is held at v ss 0.3 v, the device draws cmos standby current (i cc5 ). if reset# is held at v il but not within v ss 0.3 v, the standby current will be greater. the reset# pin may be tied to the system reset circuitry. a system reset would thus also reset the flash memory, enabling the system to read the boot-up firm- ware from the flash memory.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 29 preliminary refer to the ac characteristics tables for reset# parameters and to figure 14 for the timing diagram. output disable mode when the oe# input is at v ih , output from the device is disabled. the output pins are placed in the high impedance state.
30 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 2. s29gl032m (model r0) sector address table sector a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 000000?00ffff sa1 0 0 0 0 0 1 010000?01ffff sa2 0 0 0 0 1 0 020000?02ffff sa3 0 0 0 0 1 1 030000?03ffff sa4 0 0 0 1 0 0 040000?04ffff sa5 0 0 0 1 0 1 050000?05ffff sa6 0 0 0 1 1 0 060000?06ffff sa7 0 0 0 1 1 1 070000?07ffff sa8 0 0 1 0 0 0 080000?08ffff sa9 0 0 1 0 0 1 090000?09ffff sa10 0 0 1 0 1 0 0a0000?0affff sa11 0 0 1 0 1 1 0b0000?0bffff sa12 0 0 1 1 0 0 0c0000?0cffff sa13 0 0 1 1 0 1 0d0000?0dffff sa14 0 0 1 1 1 0 0e0000?0effff sa15 0 0 1 1 1 1 0f0000?0fffff sa16 0 1 0 0 0 0 100000?10ffff sa17 0 1 0 0 0 1 110000?11ffff sa18 0 1 0 0 1 0 120000?12ffff sa19 0 1 0 0 1 1 130000?13ffff sa20 010100 140000?14ffff sa21 010101 150000?15ffff sa22 0 1 0 1 1 0 160000?16ffff sa23 0101 1 1 170000?17ffff sa24 0 1 1 0 0 0 180000?18ffff sa25 01 1001 190000?19ffff sa26 01 1010 1a0000?1affff sa27 0 1 1 0 1 1 1b0000?1bffff sa28 0 1 1 1 0 0 1c0000?1cffff sa29 0 1 1 1 0 1 1d0000?1dffff sa30 011110 1e0000?1e ffff sa31 011111 1f0000?1 fffff sa32 1 0 0 0 0 0 200000?20ffff sa33 1 0 0 0 0 1 210000?21ffff sa34 1 0 0 0 1 0 220000?22ffff
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 31 preliminary sa35 1 0 0 0 1 1 230000?23ffff sa36 1 0 0 1 0 0 240000?24ffff sa37 1 0 0 1 0 1 250000?25ffff sa38 1 0 0 1 1 0 260000?26ffff sa39 1 0 0 1 1 1 270000?27ffff sa40 1 0 1 0 0 0 280000?28ffff sa41 1 0 1 0 0 1 290000?29ffff sa42 1 0 1 0 1 0 2a0000?2affff sa43 1 0 1 0 1 1 2b0000?2bffff sa44 1 0 1 1 0 0 2c0000?2cffff sa45 1 0 1 1 0 1 2d0000?2dffff sa46 1 0 1 1 1 0 2e0000?2effff sa47 1 0 1 1 1 1 2f0000?2fffff sa48 1 1 0 0 0 0 300000?30ffff sa49 1 1 0 0 0 1 310000?31ffff sa50 1 1 0 0 1 0 320000?32ffff sa51 1 1 0 0 1 1 330000?33ffff sa52 1 1 0 1 0 0 340000?34ffff sa53 1 10101 350000?35ffff sa54 1 1 0 1 1 0 360000?36ffff sa55 1 1 0 1 1 1 370000?37ffff sa56 1 1 1 0 0 0 380000?38ffff sa57 1 1 1 0 0 1 390000?39ffff sa58 1 1 1 0 1 0 3a0000?3affff sa59 1 1 1 0 1 1 3b0000?3bffff sa60 111100 3c0000?3c ffff sa61 111101 3d0000?3d ffff sa62 111110 3e0000?3e ffff sa63 111111 3f0000?3 fffff table 2. s29gl032m (model r0) sector address table (continued) sector a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
32 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 3. s29gl032m (models r1 , r2) sector address table sector a20-a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 64/32 000000?00ffff 000000?007fff sa1 0 0 0 0 0 1 64/32 010000?01ffff 008000?00ffff sa2 0 0 0 0 1 0 64/32 020000?02ffff 010000?017fff sa3 0 0 0 0 1 1 64/32 030000?03ffff 018000?01ffff sa4 0 0 0 1 0 0 64/32 040000?04ffff 020000?027fff sa5 0 0 0 1 0 1 64/32 050000?05ffff 028000?02ffff sa6 0 0 0 1 1 0 64/32 060000?06ffff 030000?037fff sa7 0 0 0 1 1 1 64/32 070000?07ffff 038000?03ffff sa8 0 0 1 0 0 0 64/32 080000?08ffff 040000?047fff sa9 0 0 1 0 0 1 64/32 090000?09ffff 048000?04ffff sa10 0 0 1 0 1 0 64/32 0a0000?0affff 050000?057fff sa11 0 0 1 0 1 1 64/32 0b0000?0bffff 058000?05ffff sa12 0 0 1 1 0 0 64/32 0c0000?0cffff 060000?067fff sa13 0 0 1 1 0 1 64/32 0d0000?0dffff 068000?06ffff sa14 0 0 1 1 1 0 64/32 0e0000?0effff 070000?077fff sa15 001111 64/32 0f0000?0fffff 078000?07ffff sa16 0 1 0 0 0 0 64/32 100000?10ffff 080000?087fff sa17 0 1 0 0 0 1 64/32 110000?11ffff 088000?08ffff sa18 0 1 0 0 1 0 64/32 120000?12ffff 090000?097fff sa19 0 1 0 0 1 1 64/32 130000?13ffff 098000?09ffff sa20 0 1 0 1 0 0 64/32 140000?14ffff 0a0000?0a7fff sa21 0 1 0 1 0 1 64/32 150000?15ffff 0a8000?0affff sa22 0 1 0 1 1 0 64/32 160000?16ffff 0b0000?0b7fff sa23 0 1 0 1 1 1 64/32 170000?17ffff 0b8000?0bffff sa24 0 1 1 0 0 0 64/32 180000?18ffff 0c0000?0c7fff sa25 0 1 1 0 0 1 64/32 190000?19ffff 0c8000?0cffff sa26 0 1 1 0 1 0 64/32 1a0000?1affff 0d0000?0d7fff sa27 0 1 1 0 1 1 64/32 1b0000?1bffff 0d8000?0dffff sa28 0 1 1 1 0 0 64/32 1c0000?1cffff 0e0000?0e7fff sa29 0 1 1 1 0 1 64/32 1d0000?1dffff 0e8000?0effff sa30 011110 64/32 1e0000?1effff 0f0000?0f7fff sa31 011111 64/32 1f0000?1fffff 0f8000?0fffff sa32 1 0 0 0 0 0 64/32 200000?20ffff 100000?107fff sa33 1 0 0 0 0 1 64/32 210000?21ffff 108000?10ffff sa34 1 0 0 0 1 0 64/32 220000?22ffff 110000?117fff sa35 1 0 0 0 1 1 64/32 230000?23ffff 118000?11ffff sa36 1 0 0 1 0 0 64/32 240000?24ffff 120000?127fff sa37 1 0 0 1 0 1 64/32 250000?25ffff 128000?12ffff sa38 1 0 0 1 1 0 64/32 260000?26ffff 130000?137fff sa39 1 0 0 1 1 1 64/32 270000?27ffff 138000?13ffff sa40 1 0 1 0 0 0 64/32 280000?28ffff 140000?147fff sa41 1 0 1 0 0 1 64/32 290000?29ffff 148000?14ffff sa42 1 0 1 0 1 0 64/32 2a0000?2affff 150000?157fff sa43 1 0 1 0 1 1 64/32 2b0000?2bffff 158000?15ffff sa44 1 0 1 1 0 0 64/32 2c0000?2cffff 160000?167fff
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 33 preliminary sa45 1 0 1 1 0 1 64/32 2d0000?2dffff 168000?16ffff sa46 1 0 1 1 1 0 64/32 2e0000?2effff 170000?177fff sa47 101111 64/32 2f0000?2fffff 178000?17ffff sa48 1 1 0 0 0 0 64/32 300000?30ffff 180000?187fff sa49 1 1 0 0 0 1 64/32 310000?31ffff 188000?18ffff sa50 1 1 0 0 1 0 64/32 320000?32ffff 190000?197fff sa51 1 1 0 0 1 1 64/32 330000?33ffff 198000?19ffff sa52 1 1 0 1 0 0 64/32 340000?34ffff 1a0000?1a7fff sa53 1 1 0 1 0 1 64/32 350000?35ffff 1a8000?1affff sa54 1 1 0 1 1 0 64/32 360000?36ffff 1b0000?1b7fff sa55 1 1 0 1 1 1 64/32 370000?37ffff 1b8000?1bffff sa56 1 1 1 0 0 0 64/32 380000?38ffff 1c0000?1c7fff sa57 1 1 1 0 0 1 64/32 390000?39ffff 1c8000?1cffff sa58 1 1 1 0 1 0 64/32 3a0000?3affff 1d0000?1d7fff sa59 1 1 1 0 1 1 64/32 3b0000?3bffff 1d8000?1dffff sa60 111100 64/32 3c0000?3c ffff 1e0000?1e7fff sa61 111101 64/32 3d0000?3dffff 1e8000?1effff sa62 111110 64/32 3e0000?3effff 1f0000?1f7fff sa63 111111 64/32 3f0000?3fffff 1f8000?1f ffff table 3. s29gl032m (models r1, r2) sector address table (continued) sector a20-a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
34 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 4. s29gl032m (model r3) top boot sector architecture sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa1 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa2 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa3 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa4 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa5 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa6 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa7 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa8 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa9 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa10 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa11 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa12 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa13 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa14 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa15 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa16 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa17 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa18 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa19 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa20 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa21 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa22 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa23 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa24 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa25 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa26 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa27 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa28 011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa29 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa30 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa31 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa32 100000xxx 64/32 200000 h?20ffffh f9000h?107fffh sa33 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa34 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa35 101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa36 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa37 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 35 preliminary sa38 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa39 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa40 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa41 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa42 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa43 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa44 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa45 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa46 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa47 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa48 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa49 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa50 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa51 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa52 100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa53 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa54 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa55 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa56 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa57 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa58 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa59 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa60 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa61 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa62 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa63 111111000 8/4 3f0000h?3f1fffh 1f8000h?1f8fffh sa64 111111001 8/4 3f2000h?3f3fffh 1f9000h?1f9fffh sa65 111111010 8/4 3f4000h?3f5fffh 1fa000h?1fafffh sa66 111111011 8/4 3f6000h?3f7fffh 1fb000h?1fbfffh sa67 111111100 8/4 3f8000h?3 f9fffh 1fc000h?1fcfffh sa68 111111101 8/4 3fa000h?3fbfffh 1fd000h?1fdfffh sa69 111111110 8/4 3fc000h?3fdfffh 1fe000h?1fefffh sa70 111111111 8/4 3fe000h?3fffffh 1ff000h?1fffffh table 4. s29gl032m (model r3) top boot sector architecture (continued) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
36 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 5. s29gl032m (model r4) bottom boot sector architecture sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 000000000 8/4 000000h?001fffh 00000h?00fffh sa1 000000001 8/4 002000h?003fffh 01000h?01fffh sa2 000000010 8/4 004000h?005fffh 02000h?02fffh sa3 000000011 8/4 006000h?007fffh 03000h?03fffh sa4 000000100 8/4 008000h?009fffh 04000h?04fffh sa5 000000101 8/4 00a000 h?00bfffh 05000h?05fffh sa6 000000110 8/4 00c000h?00dfffh 06000h?06fffh sa7 000000111 8/4 00e000h?00fffffh 07000h?07fffh sa8 000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa9 000010xxx 64/32 020000h?02ffffh 10000h?17fffh sa10 000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa11 000100xxx 64/32 040000h?04ffffh 20000h?27fffh sa12 000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa13 000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa14 000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa15 001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa16 001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa17 001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa18 001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa19 001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa20 001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa21 001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa22 001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa23 010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa24 010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa25 010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa26 010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa27 010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa28 010101xxx 64/32 150000h?15ffffh a8000h?affffh sa29 010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa30 010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa31 011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa32 011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa33 011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa34 011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa35 011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa36 011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa37 011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 37 preliminary sa38 011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa39 100000xxx 64/32 200000 h?20ffffh f9000h?107fffh sa40 100001xxx 64/32 210000h?21ffffh 108000h?10ffffh sa41 100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa42 101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa43 100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa44 100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa45 100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa46 100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa47 101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa48 101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa49 101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa50 101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa51 101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa52 101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa53 101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa55 110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa56 110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa57 110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa58 110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa59 100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa60 110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa61 110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa62 110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa63 111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa64 111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa65 111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa66 111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa67 111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa68 111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa69 111110xxx 64/32 3e0000h?3effffh 1f0000h?1f7fffh sa70 111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh table 5. s29gl032m (model r4) bottom boot sector architecture (continued) sector sector address a20?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
38 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 6. s29gl064m (model r0) sector address table sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal) sa0 0000000 000000?00 ffff sa1 000000 1 010000?01 ffff sa2 00000 1 0 020000?02ffff sa3 00000 1 1 030000?03 ffff sa4 0000 1 00 040000?04ffff sa5 0000 1 0 1 050000?05ffff sa6 0000 1 1 0 060000?06 ffff sa7 0000 1 1 1 070000?07ffff sa8 0 0 0 1 0 0 0 080000?08ffff sa9 0 0 0 1 0 0 1 090000?09ffff sa10 0 0 0 1 0 1 0 0a0000?0affff sa11 0 0 0 1 0 1 1 0b0000?0bffff sa12 0 0 0 1 1 0 0 0c0000?0cffff sa13 0 0 0 1 1 0 1 0d0000?0dffff sa14 0 0 0 1 1 1 0 0e0000?0effff sa15 0001111 0f0000?0 fffff sa16 00 1 0000 100000?10 ffff sa17 0 0 1 0 0 0 1 110000?11ffff sa18 0 0 1 0 0 1 0 120000?12ffff sa19 0 0 1 0 0 1 1 130000?13ffff sa20 0 0 1 0 1 0 0 140000?14ffff sa21 0 0 1 0 1 0 1 150000?15ffff sa22 0 0 1 0 1 1 0 160000?16ffff sa23 0 0 1 0 1 1 1 170000?17ffff sa24 00 1 1 000 180000?18ffff sa25 0 0 1 1 0 0 1 190000?19ffff sa26 0 0 1 1 0 1 0 1a0000?1affff sa27 0 0 1 1 0 1 1 1b0000?1bffff sa28 0 0 1 1 1 0 0 1c0000?1cffff sa29 0 0 1 1 1 0 1 1d0000?1dffff sa30 0 0 1 1 1 1 0 1e0000?1effff sa31 0011111 1f0000?1f ffff sa32 0 1 00000 200000?20ffff sa33 0 1 0000 1 210000?21ffff sa34 0 1 0 0 0 1 0 220000?22ffff
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 39 preliminary sa35 0 1 0 0 0 1 1 230000?23ffff sa36 0 1 0 0 1 0 0 240000?24ffff sa37 0 1 0 0 1 0 1 250000?25ffff sa38 0 1 0 0 1 1 0 260000?26ffff sa39 0 1 0 0 1 1 1 270000?27ffff sa40 0 1 0 1 0 0 0 280000?28ffff sa41 0 1 0 1 0 0 1 290000?29ffff sa42 0 1 0 1 0 1 0 2a0000?2affff sa43 0 1 0 1 0 1 1 2b0000?2bffff sa44 0 1 0 1 1 0 0 2c0000?2cffff sa45 0 1 0 1 1 0 1 2d0000?2dffff sa46 0 1 0 1 1 1 0 2e0000?2effff sa47 0101111 2f0000?2 fffff sa48 0 1 1 0000 300000?30 ffff sa49 0 1 1 0 0 0 1 310000?31ffff sa50 0 1 1 0 0 1 0 320000?32ffff sa51 0 1 1 0 0 1 1 330000?33ffff sa52 0 1 1 0 1 0 0 340000?34ffff sa53 0 1 1 0 1 0 1 350000?35ffff sa54 0 1 1 0 1 1 0 360000?36ffff sa55 0 1 1 0 1 1 1 370000?37ffff sa56 0 1 1 1 0 0 0 380000?38ffff sa57 0 1 1 1 0 0 1 390000?39ffff sa58 0 1 1 1 0 1 0 3a0000?3affff sa59 0 1 1 1 0 1 1 3b0000?3bffff sa60 0 1 1 1 1 0 0 3c0000?3cffff sa61 0 1 1 1 1 0 1 3d0000?3dffff sa62 0 1 1 1 1 1 0 3e0000?3effff sa63 0111111 3f0000?3f ffff sa64 1 000000 400000?40ffff sa65 1 00000 1 410000?41 ffff sa66 1 0000 1 0 420000?42 ffff sa67 1 0000 1 1 430000?43 ffff sa68 1 0 0 0 1 0 0 440000?44ffff sa69 1 0 0 0 1 0 1 450000?45ffff table 6. s29gl064m (model r0) sector address table (continued) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
40 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa70 1 0 0 0 1 1 0 460000?46ffff sa71 1 0 0 0 1 1 1 470000?47ffff sa72 1 0 0 1 0 0 0 480000?48ffff sa73 1 0 0 1 0 0 1 490000?49ffff sa74 1 0 0 1 0 1 0 4a0000?4affff sa75 1 0 0 1 0 1 1 4b0000?4bffff sa76 1 0 0 1 1 0 0 4c0000?4cffff sa77 1 0 0 1 1 0 1 4d0000?4dffff sa78 1 0 0 1 1 1 0 4e0000?4effff sa79 1001111 4f0000?4 fffff sa80 1 0 1 0000 500000?50ffff sa81 1 0 1 0 0 0 1 510000?51ffff sa82 1 0 1 0 0 1 0 520000?52ffff sa83 1 0 1 0 0 1 1 530000?53ffff sa84 1010100 540000?54ffff sa85 1010101 550000?55ffff sa86 1 0 1 0 1 1 0 560000?56ffff sa87 1 0 1 0 1 1 1 570000?57ffff sa88 1 0 1 1 0 0 0 580000?58ffff sa89 1 0 1 1 0 0 1 590000?59ffff sa90 1 0 1 1 0 1 0 5a0000?5affff sa91 1 0 1 1 0 1 1 5b0000?5bffff sa92 1 0 1 1 1 0 0 5c0000?5cffff sa93 1 0 1 1 1 0 1 5d0000?5dffff sa94 1 0 1 1 1 1 0 5e0000?5effff sa95 1011111 5f0000?5 fffff sa96 1 1 00000 600000?60 ffff sa97 1 1 0000 1 610000?61 ffff sa98 1 1 0 0 0 1 0 620000?62ffff sa99 1 1 0 0 0 1 1 630000?63ffff sa100 1 1 0 0 1 0 0 640000?64ffff sa101 1 1 0 0 1 0 1 650000?65ffff sa102 1 1 0 0 1 1 0 660000?66ffff sa103 1 1 0 0 1 1 1 670000?67ffff sa104 1 1 0 1 0 0 0 680000?68ffff table 6. s29gl064m (model r0) sector address table (continued) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 41 preliminary sa105 1 1 0 1 0 0 1 690000?69ffff sa106 1 1 0 1 0 1 0 6a0000?6affff sa107 1 1 0 1 0 1 1 6b0000?6bffff sa108 1 1 0 1 1 0 0 6c0000?6cffff sa109 1 1 0 1 1 0 1 6d0000?6dffff sa110 1 1 0 1 1 1 0 6e0000?6effff sa111 1101111 6f0000?6f ffff sa112 1 1 1 0000 700000?70ffff sa113 1 1 1 0 0 0 1 710000?71ffff sa114 1 1 1 0 0 1 0 720000?72ffff sa115 1 1 1 0 0 1 1 730000?73ffff sa116 1 1 1 0 1 0 0 740000?74ffff sa117 1 1 1 0 1 0 1 750000?75ffff sa118 1 1 1 0 1 1 0 760000?76ffff sa119 1110111 770000?77ffff sa120 1 1 1 1 0 0 0 780000?78ffff sa121 1 1 1 1 0 0 1 790000?79ffff sa122 1 1 1 1 0 1 0 7a0000?7affff sa123 1 1 1 1 0 1 1 7b0000?7bffff sa124 1 1 1 1 1 0 0 7c0000?7cffff sa125 1 1 1 1 1 0 1 7d0000?7dffff sa126 1 1 1 1 1 1 0 7e0000?7effff sa127 1111111 7f0000?7 fffff table 6. s29gl064m (model r0) sector address table (continued) sector a22 a21 a20 a19 a18 a17 a16 8-bit address range (in hexadecimal)
42 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 7. s29gl064m (models r1, r2) sector address table sector a21?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 0000000 64/32 0 00000?00ffff 000000?007fff sa1 000000 1 64/32 010000?01ffff 008 000?00ffff sa2 00000 1 0 64/32 020000?02ffff 01 0000?017fff sa3 00000 1 1 64/32 030000?03ffff 018 000?01ffff sa4 0000 1 00 64/32 040000?04 ffff 02 0000?027fff sa5 0000 1 0 1 64/32 050000?05ffff 028 000?02ffff sa6 0000 1 1 0 64/32 060000?06ffff 03 0000?037fff sa7 0000 1 1 1 64/32 070000?07ffff 038 000?03ffff sa8 0 0 0 1 0 0 0 64/32 080000?08ffff 040000?047fff sa9 0 0 0 1 0 0 1 64/32 090000?09ffff 048000?04ffff sa10 0 0 0 1 0 1 0 64/32 0a0000?0affff 050000?057fff sa11 0 0 0 1 0 1 1 64/32 0b0000?0bffff 058000?05ffff sa12 0 0 0 1 1 0 0 64/32 0c0000?0cffff 060000?067fff sa13 0 0 0 1 1 0 1 64/32 0d0000?0dffff 068000?06ffff sa14 0 0 0 1 1 1 0 64/32 0e0000?0effff 070000?077fff sa15 0001111 64/32 0f0000?0fffff 078 000?07ffff sa16 00 1 0000 64/32 1 00000?10ffff 080000?087fff sa17 0 0 1 0 0 0 1 64/32 110000?11ffff 088000?08ffff sa18 0 0 1 0 0 1 0 64/32 120000?12ffff 090000?097fff sa19 0 0 1 0 0 1 1 64/32 130000?13ffff 098000?09ffff sa20 0 0 1 0 1 0 0 64/32 140000?14ffff 0a0000?0a7fff sa21 0 0 1 0 1 0 1 64/32 150000?15ffff 0a8000?0affff sa22 0 0 1 0 1 1 0 64/32 160000?16ffff 0b0000?0b7fff sa23 0 0 1 0 1 1 1 64/32 170000?17ffff 0b8000?0bffff sa24 0 0 1 1 0 0 0 64/32 180000?18ffff 0c0000?0c7fff sa25 0 0 1 1 0 0 1 64/32 190000?19ffff 0c8000?0cffff sa26 0 0 1 1 0 1 0 64/32 1a0000?1affff 0d0000?0d7fff sa27 0 0 1 1 0 1 1 64/32 1b0000?1bffff 0d8000?0dffff sa28 0 0 1 1 1 0 0 64/32 1c0000?1cffff 0e0000?0e7fff sa29 0 0 1 1 1 0 1 64/32 1d0000?1dffff 0e8000?0effff sa30 0011110 64/32 1e0000?1effff 0f 0000?0f7fff sa31 0011111 64/32 1f0000?1fffff 0f8 000?0 fffff sa32 0 1 00000 64/32 2 00000?20ffff 100000?107fff sa33 0 1 0000 1 64/32 210000?21ffff 108 000?10ffff sa34 0 1 0 0 0 1 0 64/32 220000?22ffff 110000?117fff
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 43 preliminary sa35 0 1 0 0 0 1 1 64/32 230000?23ffff 118000?11ffff sa36 0 1 0 0 1 0 0 64/32 240000?24ffff 120000?127fff sa37 0 1 0 0 1 0 1 64/32 25000 0?25ffff 12 8000? 12ffff sa38 0 1 0 0 1 1 0 64/32 26 0000?26 ffff 130000 ?137fff sa39 0 1 0 0 1 1 1 64/32 270000?27ffff 138000?13ffff sa40 0 1 0 1 0 0 0 64/32 28000 0?28ffff 140000?147fff sa41 0 1 0 1 0 0 1 64/32 290000?29ffff 148000?14ffff sa42 0 1 0 1 0 1 0 64/32 2a0000?2affff 150000?157fff sa43 0 1 0 1 0 1 1 64/32 2b0000?2bffff 158000?15ffff sa44 0 1 0 1 1 0 0 64/32 2c0000?2cffff 160000?167fff sa45 0 1 0 1 1 0 1 64/32 2d0000?2dffff 168000?16ffff sa46 0 1 0 1 1 1 0 64/32 2e0000?2effff 170000?177fff sa47 0101111 64/32 2f0000?2f ffff 178 000?17ffff sa48 0 1 1 0000 64/32 3 00000?30ffff 180000?187fff sa49 0 1 1 0 0 0 1 64/32 310000?31ffff 188000?18ffff sa50 0 1 1 0 0 1 0 64/32 320000?32ffff 190000?197fff sa51 0 1 1 0 0 1 1 64/32 330000?33ffff 198000?19ffff sa52 0 1 1 0 1 0 0 64/32 340000?34ffff 1a0000?1a7fff sa53 0 1 1 0 1 0 1 64/32 350000?35ffff 1a8000?1affff sa54 0 1 1 0 1 1 0 64/32 360000?36ffff 1b0000?1b7fff sa55 0 1 1 0 1 1 1 64/32 370000?37ffff 1b8000?1bffff sa56 0 1 1 1 0 0 0 64/32 380000?38ffff 1c0000?1c7fff sa57 0 1 1 1 0 0 1 64/32 390000?39ffff 1c8000?1cffff sa58 0 1 1 1 0 1 0 64/32 3a0000?3affff 1d0000?1d7fff sa59 0 1 1 1 0 1 1 64/32 3b0000?3bffff 1d8000?1dffff sa60 0 1 1 1 1 0 0 64/32 3c0000?3cffff 1e0000?1e7fff sa61 0 1 1 1 1 0 1 64/32 3d0000?3dffff 1e8000?1effff sa62 0111110 64/32 3e0000?3effff 1f 0000?1f7fff sa63 0111111 64/32 3f0000?3 fffff 1f8 000?1 fffff sa64 1 000000 64/32 4 00000?40 ffff 20 0000?207fff sa65 1 00000 1 64/32 410000?41ffff 208 000?20ffff sa66 1 0000 1 0 64/32 420000?42ffff 21 0000?217fff sa67 1 0000 1 1 64/32 430000?43ffff 218 000?21ffff sa68 1 0 0 0 1 0 0 64/32 440000?44ffff 220000?227fff sa69 1 0 0 0 1 0 1 64/32 450000?45ffff 228000?22ffff sa70 1 0 0 0 1 1 0 64/32 460000?46ffff 230000?237fff table 7. s29gl064m (models r1, r2) sector address table (continued) sector a21?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
44 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa71 1 0 0 0 1 1 1 64/32 470000?47ffff 238000?23ffff sa72 1 0 0 1 0 0 0 64/32 480000?48ffff 240000?247fff sa73 1 0 0 1 0 0 1 64/32 490000?49ffff 248000?24ffff sa74 1 0 0 1 0 1 0 64/32 4a0000?4affff 250000?257fff sa75 1 0 0 1 0 1 1 64/32 4b0000?4bffff 258000?25ffff sa76 1 0 0 1 1 0 0 64/32 4c0000?4cffff 260000?267fff sa77 1 0 0 1 1 0 1 64/32 4d0000?4dffff 268000?26ffff sa78 1 0 0 1 1 1 0 64/32 4e0000?4effff 270000?277fff sa79 1001111 64/32 4f0000?4fffff 278 000?27ffff sa80 1 0 1 0000 64/32 5 00000?50ffff 280000?287fff sa81 1 0 1 0 0 0 1 64/32 510000?51ffff 288000?28ffff sa82 1 0 1 0 0 1 0 64/32 520000?52ffff 290000?297fff sa83 1 0 1 0 0 1 1 64/32 530000?53ffff 298000?29ffff sa84 1 0 1 0 1 0 0 64/32 540000?54ffff 2a0000?2a7fff sa85 1 0 1 0 1 0 1 64/32 55 0000?55ffff 2a8000?2affff sa86 1 0 1 0 1 1 0 64/32 560000?56ffff 2b0000?2b7fff sa87 1 0 1 0 1 1 1 64/32 570000?57ffff 2b8000?2bffff sa88 1 0 1 1 0 0 0 64/32 580000?58ffff 2c0000?2c7fff sa89 1 0 1 1 0 0 1 64/32 590000?59ffff 2c8000?2cffff sa90 1 0 1 1 0 1 0 64/32 5a0000?5affff 2d0000?2d7fff sa91 1 0 1 1 0 1 1 64/32 5b0000?5bffff 2d8000?2dffff sa92 1 0 1 1 1 0 0 64/32 5c0000?5cffff 2e0000?2e7fff sa93 1 0 1 1 1 0 1 64/32 5d0000?5dffff 2e8000?2effff sa94 1011110 64/32 5e0000?5effff 2f 0000?2f7fff sa95 1011111 64/32 5f0000?5fffff 2f8 000?2fffff sa96 1 1 00000 64/32 6 00000?60ffff 300000?307fff sa97 1 1 0000 1 64/32 610000?61ffff 308 000?30ffff sa98 1 1 0 0 0 1 0 64/32 620000?62ffff 310000?317fff sa99 1 1 0 0 0 1 1 64/32 630000?63ffff 318000?31ffff sa100 1 1 0 0 1 0 0 64/32 640000?64ffff 320000?327fff sa101 1 1 0 0 1 0 1 64/32 650000?65ffff 328000?32ffff sa102 1 1 0 0 1 1 0 64/32 660000?66ffff 330000?337fff sa103 1 1 0 0 1 1 1 64/32 670000?67ffff 338000?33ffff sa104 1 1 0 1 0 0 0 64/32 680000?68ffff 340000?347fff sa105 1 1 0 1 0 0 1 64/32 690000?69ffff 348000?34ffff sa106 1 1 0 1 0 1 0 64/32 6a0000?6affff 350000?357fff table 7. s29gl064m (models r1, r2) sector address table (continued) sector a21?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 45 preliminary sa107 1 1 0 1 0 1 1 64/32 6b0000?6bffff 358000?35ffff sa108 1 1 0 1 1 0 0 64/32 6c0000?6cffff 360000?367fff sa109 1 1 0 1 1 0 1 64/32 6d0000?6dffff 368000?36ffff sa110 1 1 0 1 1 1 0 64/32 6e0000?6effff 370000?377fff sa111 1101111 64/32 6f0000?6fffff 378 000?37ffff sa112 1 1 1 0000 64/32 7 00000?70ffff 380000?387fff sa113 1 1 1 0 0 0 1 64/32 710000?71ffff 388000?38ffff sa114 1 1 1 0 0 1 0 64/32 720000?72ffff 390000?397fff sa115 1 1 1 0 0 1 1 64/32 73 0000?73ffff 3 98000? 39ffff sa116 1 1 1 0 1 0 0 64/32 740000?74ffff 3a0000?3a7fff sa117 1 1 1 0 1 0 1 64/32 750000?75ffff 3a8000?3affff sa118 1 1 1 0 1 1 0 64/32 760000?76ffff 3b0000?3b7fff sa119 1 1 1 0 1 1 1 64/32 770000?77ffff 3b8000?3bffff sa120 1 1 1 1 0 0 0 64/32 780000?78ffff 3c0000?3c7fff sa121 1 1 1 1 0 0 1 64/32 790000?79ffff 3c8000?3cffff sa122 1 1 1 1 0 1 0 64/32 7a0000?7affff 3d0000?3d7fff sa123 1 1 1 1 0 1 1 64/32 7b0000?7bffff 3d8000?3dffff sa124 1 1 1 1 1 0 0 64/32 7c0000?7cffff 3e0000?3e7fff sa125 1 1 1 1 1 0 1 64/32 7d0000?7dffff 3e8000?3effff sa126 1111110 64/32 7e0000?7effff 3f 0000?3f7fff sa127 1111111 64/32 7f0000?7fffff 3f8 000?3fffff table 7. s29gl064m (models r1, r2) sector address table (continued) sector a21?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
46 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 8. s29gl064m (model r3) top boot sector architecture sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 0000000xxx 64/32 000000h?00ffffh 00000h?07fffh sa1 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa2 0000010xxx 64/32 020000 h?02ffffh 10000h?17fffh sa3 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa4 0000100xxx 64/32 040000 h?04ffffh 20000h?27fffh sa5 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa6 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa7 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa8 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa9 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa10 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa11 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa12 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa13 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa14 0001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa15 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa16 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa17 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa18 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa19 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa20 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa21 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa22 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa23 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa24 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa25 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa26 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa27 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa28 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa29 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa30 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa31 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh sa32 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa33 0100001xxx 64/32 210000 h?21ffffh 108000h?10ffffh sa34 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa35 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa36 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa37 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 47 preliminary sa38 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa39 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa40 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa41 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa42 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa43 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa44 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa45 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa46 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa47 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa48 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa49 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa50 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa51 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa52 0100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa53 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa54 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa55 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa56 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa57 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa58 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa59 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa60 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa61 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa62 0111110xxx 64/32 3e0000 h?3effffh 1f0000h?1f7fffh sa63 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa64 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa65 1000001xxx 64/32 410000 h?41ffffh 208000h?20ffffh sa66 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa67 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa68 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa69 1000101xxx 64/32 450000h?45ffffh 228000h?22ffffh sa70 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh sa71 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa72 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa73 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa74 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa75 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa76 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh table 8. s29gl064m (model r3) top boot sector architecture (continued) sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
48 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa77 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa78 1001110xxx 64/32 4e0000 h?4effffh 270000h?277fffh sa79 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa80 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa81 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa82 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa83 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa84 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa85 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa86 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa87 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa88 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa89 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa90 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa91 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa92 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa93 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa94 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa95 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa96 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa97 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa98 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa99 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa100 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa101 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa102 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa103 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa104 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa105 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa106 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa107 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa108 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa109 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh sa110 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa111 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa112 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa113 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa114 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa115 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh table 8. s29gl064m (model r3) top boot sector architecture (continued) sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 49 preliminary sa116 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa117 1110101xxx 64/32 750000 h?75ffffh 3a8 000h?3affffh sa118 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa119 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa120 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa121 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa122 1111010xxx 64/32 7a0000 h?7affffh 3d0000h?3d7fffh sa123 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa124 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa125 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa126 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa127 1111111000 8/4 7f0000h?7f1fffh 3f8000h?3f8fffh sa128 1111111001 8/4 7f2000h?7f3fffh 3f9000h?3f9fffh sa129 1111111010 8/4 7f4000h?7f5fffh 3fa000h?3fafffh sa130 1111111011 8/4 7f6000h?7f7fffh 3fb000h?3fbfffh sa131 1111111100 8/4 7f8000h?7f9fffh 3fc000h?3fcfffh sa132 1111111101 8/4 7fa000h?7fbfffh 3fd000h?3fdfffh sa133 1111111110 8/4 7fc000h?7fdfffh 3fe000h?3fefffh sa134 1111111111 8/4 7fe000h?7 fffffh 3ff000h?3fffffh table 8. s29gl064m (model r3) top boot sector architecture (continued) sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
50 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 9. s29gl064m (model r4) bottom boot sector architecture sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range sa0 0000000000 8/4 000000h?001fffh 00000h?00fffh sa1 0000000001 8/4 002000h?003fffh 01000h?01fffh sa2 0000000010 8/4 004000h?005fffh 02000h?02fffh sa3 0000000011 8/4 006000h?007fffh 03000h?03fffh sa4 0000000100 8/4 008000h?009fffh 04000h?04fffh sa5 0000000101 8/4 00a000 h?00bfffh 05000h?05fffh sa6 0000000110 8/4 00c000h?00dfffh 06000h?06fffh sa7 0000000111 8/4 00e000h?00fffffh 07000h?07fffh sa8 0000001xxx 64/32 010000h?01ffffh 08000h?0ffffh sa9 0000010xxx 64/32 020000 h?02ffffh 10000h?17fffh sa10 0000011xxx 64/32 030000h?03ffffh 18000h?1ffffh sa11 0000100xxx 64/32 040000 h?04ffffh 20000h?27fffh sa12 0000101xxx 64/32 050000h?05ffffh 28000h?2ffffh sa13 0000110xxx 64/32 060000h?06ffffh 30000h?37fffh sa14 0000111xxx 64/32 070000h?07ffffh 38000h?3ffffh sa15 0001000xxx 64/32 080000h?08ffffh 40000h?47fffh sa16 0001001xxx 64/32 090000h?09ffffh 48000h?4ffffh sa17 0001010xxx 64/32 0a0000h?0affffh 50000h?57fffh sa18 0001011xxx 64/32 0b0000h?0bffffh 58000h?5ffffh sa19 0001100xxx 64/32 0c0000h?0cffffh 60000h?67fffh sa20 0001101xxx 64/32 0d0000h?0dffffh 68000h?6ffffh sa21 0001101xxx 64/32 0e0000h?0effffh 70000h?77fffh sa22 0001111xxx 64/32 0f0000h?0fffffh 78000h?7ffffh sa23 0010000xxx 64/32 100000h?00ffffh 80000h?87fffh sa24 0010001xxx 64/32 110000h?11ffffh 88000h?8ffffh sa25 0010010xxx 64/32 120000h?12ffffh 90000h?97fffh sa26 0010011xxx 64/32 130000h?13ffffh 98000h?9ffffh sa27 0010100xxx 64/32 140000h?14ffffh a0000h?a7fffh sa28 0010101xxx 64/32 150000h?15ffffh a8000h?affffh sa29 0010110xxx 64/32 160000h?16ffffh b0000h?b7fffh sa30 0010111xxx 64/32 170000h?17ffffh b8000h?bffffh sa31 0011000xxx 64/32 180000h?18ffffh c0000h?c7fffh sa32 0011001xxx 64/32 190000h?19ffffh c8000h?cffffh sa33 0011010xxx 64/32 1a0000h?1affffh d0000h?d7fffh sa34 0011011xxx 64/32 1b0000h?1bffffh d8000h?dffffh sa35 0011000xxx 64/32 1c0000h?1cffffh e0000h?e7fffh sa36 0011101xxx 64/32 1d0000h?1dffffh e8000h?effffh sa37 0011110xxx 64/32 1e0000h?1effffh f0000h?f7fffh sa38 0011111xxx 64/32 1f0000h?1fffffh f8000h?fffffh
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 51 preliminary sa39 0100000xxx 64/32 200000h?20ffffh f9000h?107fffh sa40 0100001xxx 64/32 210000 h?21ffffh 108000h?10ffffh sa41 0100010xxx 64/32 220000h?22ffffh 110000h?117fffh sa42 0101011xxx 64/32 230000h?23ffffh 118000h?11ffffh sa43 0100100xxx 64/32 240000h?24ffffh 120000h?127fffh sa44 0100101xxx 64/32 250000h?25ffffh 128000h?12ffffh sa45 0100110xxx 64/32 260000h?26ffffh 130000h?137fffh sa46 0100111xxx 64/32 270000h?27ffffh 138000h?13ffffh sa47 0101000xxx 64/32 280000h?28ffffh 140000h?147fffh sa48 0101001xxx 64/32 290000h?29ffffh 148000h?14ffffh sa49 0101010xxx 64/32 2a0000h?2affffh 150000h?157fffh sa50 0101011xxx 64/32 2b0000h?2bffffh 158000h?15ffffh sa51 0101100xxx 64/32 2c0000h?2cffffh 160000h?167fffh sa52 0101101xxx 64/32 2d0000h?2dffffh 168000h?16ffffh sa53 0101110xxx 64/32 2e0000h?2effffh 170000h?177fffh sa54 0101111xxx 64/32 2f0000h?2fffffh 178000h?17ffffh sa55 0110000xxx 64/32 300000h?30ffffh 180000h?187fffh sa56 0110001xxx 64/32 310000h?31ffffh 188000h?18ffffh sa57 0110010xxx 64/32 320000h?32ffffh 190000h?197fffh sa58 0110011xxx 64/32 330000h?33ffffh 198000h?19ffffh sa59 0100100xxx 64/32 340000h?34ffffh 1a0000h?1a7fffh sa60 0110101xxx 64/32 350000h?35ffffh 1a8000h?1affffh sa61 0110110xxx 64/32 360000h?36ffffh 1b0000h?1b7fffh sa62 0110111xxx 64/32 370000h?37ffffh 1b8000h?1bffffh sa63 0111000xxx 64/32 380000h?38ffffh 1c0000h?1c7fffh sa64 0111001xxx 64/32 390000h?39ffffh 1c8000h?1cffffh sa65 0111010xxx 64/32 3a0000h?3affffh 1d0000h?1d7fffh sa66 0111011xxx 64/32 3b0000h?3bffffh 1d8000h?1dffffh sa67 0111100xxx 64/32 3c0000h?3cffffh 1e0000h?1e7fffh sa68 0111101xxx 64/32 3d0000h?3dffffh 1e8000h?1effffh sa69 0111110xxx 64/32 3e0000 h?3effffh 1f0000h?1f7fffh sa70 0111111xxx 64/32 3f0000h?3fffffh 1f8000h?1fffffh sa71 1000000xxx 64/32 400000h?40ffffh 200000h?207fffh sa72 1000001xxx 64/32 410000 h?41ffffh 208000h?20ffffh sa73 1000010xxx 64/32 420000h?42ffffh 210000h?217fffh sa74 1000011xxx 64/32 430000h?43ffffh 218000h?21ffffh sa75 1000100xxx 64/32 440000h?44ffffh 220000h?227fffh sa76 1000101xxx 64/32 450000 h?45ffffh 228000h?22ffffh sa77 1000110xxx 64/32 460000h?46ffffh 230000h?237fffh table 9. s29gl064m (model r4) bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
52 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa78 1000111xxx 64/32 470000h?47ffffh 238000h?23ffffh sa79 1001000xxx 64/32 480000h?48ffffh 240000h?247fffh sa80 1001001xxx 64/32 490000h?49ffffh 248000h?24ffffh sa81 1001010xxx 64/32 4a0000h?4affffh 250000h?257fffh sa82 1001011xxx 64/32 4b0000h?4bffffh 258000h?25ffffh sa83 1001100xxx 64/32 4c0000h?4cffffh 260000h?267fffh sa84 1001101xxx 64/32 4d0000h?4dffffh 268000h?26ffffh sa85 1001110xxx 64/32 4e0000h?4effffh 270000h?277fffh sa86 1001111xxx 64/32 4f0000h?4fffffh 278000h?27ffffh sa87 1010000xxx 64/32 500000h?50ffffh 280000h?28ffffh sa88 1010001xxx 64/32 510000h?51ffffh 288000h?28ffffh sa89 1010010xxx 64/32 520000h?52ffffh 290000h?297fffh sa90 1010011xxx 64/32 530000h?53ffffh 298000h?29ffffh sa91 1010100xxx 64/32 540000h?54ffffh 2a0000h?2a7fffh sa92 1010101xxx 64/32 550000h?55ffffh 2a8000h?2affffh sa93 1010110xxx 64/32 560000h?56ffffh 2b0000h?2b7fffh sa94 1010111xxx 64/32 570000h?57ffffh 2b8000h?2bffffh sa95 1011000xxx 64/32 580000h?58ffffh 2c0000h?2c7fffh sa96 1011001xxx 64/32 590000h?59ffffh 2c8000h?2cffffh sa97 1011010xxx 64/32 5a0000h?5affffh 2d0000h?2d7fffh sa98 1011011xxx 64/32 5b0000h?5bffffh 2d8000h?2dffffh sa99 1011100xxx 64/32 5c0000h?5cffffh 2e0000h?2e7fffh sa100 1011101xxx 64/32 5d0000h?5dffffh 2e8000h?2effffh sa101 1011110xxx 64/32 5e0000h?5effffh 2f0000h?2fffffh sa102 1011111xxx 64/32 5f0000h?5fffffh 2f8000h?2fffffh sa103 1100000xxx 64/32 600000h?60ffffh 300000h?307fffh sa104 1100001xxx 64/32 610000h?61ffffh 308000h?30ffffh sa105 1100010xxx 64/32 620000h?62ffffh 310000h?317fffh sa106 1100011xxx 64/32 630000h?63ffffh 318000h?31ffffh sa107 1100100xxx 64/32 640000h?64ffffh 320000h?327fffh sa108 1100101xxx 64/32 650000h?65ffffh 328000h?32ffffh sa109 1100110xxx 64/32 660000h?66ffffh 330000h?337fffh sa110 1100111xxx 64/32 670000h?67ffffh 338000h?33ffffh sa111 1101000xxx 64/32 680000h?68ffffh 340000h?347fffh sa112 1101001xxx 64/32 690000h?69ffffh 348000h?34ffffh sa113 1101010xxx 64/32 6a0000h?6affffh 350000h?357fffh sa114 1101011xxx 64/32 6b0000h?6bffffh 358000h?35ffffh sa115 1101100xxx 64/32 6c0000h?6cffffh 360000h?367fffh sa116 1101101xxx 64/32 6d0000h?6dffffh 368000h?36ffffh table 9. s29gl064m (model r4) bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 53 preliminary sa117 1101110xxx 64/32 6e0000h?6effffh 370000h?377fffh sa118 1101111xxx 64/32 6f0000h?6fffffh 378000h?37ffffh sa119 1110000xxx 64/32 700000h?70ffffh 380000h?387fffh sa120 1110001xxx 64/32 710000h?71ffffh 388000h?38ffffh sa121 1110010xxx 64/32 720000h?72ffffh 390000h?397fffh sa122 1110011xxx 64/32 730000h?73ffffh 398000h?39ffffh sa123 1110100xxx 64/32 740000h?74ffffh 3a0000h?3a7fffh sa124 1110101xxx 64/32 750 000h?75ffffh 3a8000h?3affffh sa125 1110110xxx 64/32 760000h?76ffffh 3b0000h?3b7fffh sa126 1110111xxx 64/32 770000h?77ffffh 3b8000h?3bffffh sa127 1111000xxx 64/32 780000h?78ffffh 3c0000h?3c7fffh sa128 1111001xxx 64/32 790000h?79ffffh 3c8000h?3cffffh sa129 1111010xxx 64/32 7a0000 h?7affffh 3d0000h?3d7fffh sa130 1111011xxx 64/32 7b0000h?7bffffh 3d8000h?3dffffh sa131 1111100xxx 64/32 7c0000h?7cffffh 3e0000h?3e7fffh sa132 1111101xxx 64/32 7d0000h?7dffffh 3e8000h?3effffh sa133 1111110xxx 64/32 7e0000h?7effffh 3f0000h?3f7fffh sa134 1111111000 64/32 7f0000h?7fffffh 3f8000h?3fffffh table 10. s29gl064m (model r5) sector address table sector a21?a15 16-bit address range (in hexadecimal) sa0 0000000 0 00000?007fff sa1 000000 1 008000?00ffff sa2 00000 1 0 010000?017fff sa3 00000 1 1 018000?01ffff sa4 0000 1 00 020000?027fff sa5 0000 1 0 1 028000?02ffff sa6 0000 1 1 0 030000?037fff sa7 0000 1 1 1 038000?03ffff sa8 0 0 0 1 0 0 0 040000?047fff sa9 000 1 00 1 048000?04ffff sa10 0 0 0 1 0 1 0 050000?057fff sa11 0 0 0 1 0 1 1 058000?05ffff sa12 0 0 0 1 1 0 0 060000?067fff sa13 000 1 1 0 1 068000?06ffff sa14 0 0 0 1 1 1 0 070000?077fff sa15 0001111 078000?07ffff sa16 0 0 1 0 0 0 0 080000?087fff sa17 0 0 1 0 0 0 1 088000?08ffff sa18 0 0 1 0 0 1 0 090000?097fff table 9. s29gl064m (model r4) bottom boot sector architecture (continued) sector sector address a21?a12 sector size (kbytes/kwords) (x8) address range (x16) address range
54 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa19 0 0 1 0 0 1 1 098000?09ffff sa20 0 0 1 0 1 0 0 0a0000?0a7fff sa21 0 0 1 0 1 0 1 0a8000?0affff sa22 0 0 1 0 1 1 0 0b0000?0b7fff sa23 0 0 1 0 1 1 1 0b8000?0bffff sa24 0 0 1 1 0 0 0 0c0000?0c7fff sa25 0 0 1 1 0 0 1 0c8000?0cffff sa26 0 0 1 1 0 1 0 0d0000?0d7fff sa27 0 0 1 1 0 1 1 0d8000?0dffff sa28 0 0 1 1 1 0 0 0e0000?0e7fff sa29 0 0 1 1 1 0 1 0e8000?0effff sa30 0011110 0f0000?0f7fff sa31 0011111 0f8000?0fffff sa64 1 000000 2 00000?207fff sa65 1 00000 1 208000?20ffff sa66 1 0000 1 0 210000?217fff sa67 1 0000 1 1 218000?21ffff sa68 1 0 0 0 1 0 0 220000?227fff sa69 1 0 0 0 1 0 1 228000?22ffff sa70 1 0 0 0 1 1 0 230000?237fff sa71 1 0 0 0 1 1 1 238000?23ffff sa72 1 0 0 1 0 0 0 240000?247fff sa73 1 0 0 1 0 0 1 248000?24ffff sa74 1 0 0 1 0 1 0 250000?257fff sa75 1 0 0 1 0 1 1 258000?25ffff sa76 1 0 0 1 1 0 0 260000?267fff sa77 1001 101 268000?26ffff sa78 1 0 0 1 1 1 0 270000?277fff sa79 1001111 278000?27ffff sa80 1 0 1 0 0 0 0 280000?287fff sa81 1 0 1 0 0 0 1 288000?28ffff sa82 1 0 1 0 0 1 0 290000?297fff sa83 1 0 1 0 0 1 1 298000?29ffff sa84 1 0 1 0 1 0 0 2a0000?2a7fff sa85 1010101 2a8000?2affff sa86 1 0 1 0 1 1 0 2b0000?2b7fff sa87 1010111 2b8000?2bffff sa88 1 0 1 1 0 0 0 2c0000?2c7fff sa89 1 0 1 1 0 0 1 2c8000?2cffff sa90 1 0 1 1 0 1 0 2d0000?2d7fff sa91 1 0 1 1 0 1 1 2d8000?2dffff sa92 1 0 1 1 1 0 0 2e0000?2e7fff sa93 1 0 1 1 1 0 1 2e8000?2effff sa94 1011110 2f0000?2f7fff sa95 1011111 2f8000?2fffff table 10. s29gl064m (model r5) sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 55 preliminary sa32 0 1 0 0 0 0 0 100000?107fff sa33 0 1 0 0 0 0 1 108000?10ffff sa34 0 1 0 0 0 1 0 110000?117fff sa35 0 1 0 0 0 1 1 118000?11ffff sa36 0 1 0 0 1 0 0 120000?127fff sa37 0 1 0 0 1 0 1 128000?12ffff sa38 0 1 0 0 1 1 0 130000?137fff sa39 0100111 138000?13ffff sa40 0 1 0 1 0 0 0 140000?147fff sa41 0 1 0 1 0 0 1 148000?14ffff sa42 0101010 150000?157fff sa43 010101 1 158000?15ffff sa44 0 1 0 1 1 0 0 160000?167fff sa45 0101 101 168000?16ffff sa46 0 1 0 1 1 1 0 170000?177fff sa47 0101111 178000?17ffff sa48 0 1 1 0 0 0 0 180000?187fff sa49 0 1 1 0 0 0 1 188000?18ffff sa50 0 1 1 0 0 1 0 190000?197fff sa51 01 1001 1 198000?19ffff sa52 0 1 1 0 1 0 0 1a0000?1a7fff sa53 0 1 1 0 1 0 1 1a8000?1affff sa54 0 1 1 0 1 1 0 1b0000?1b7fff sa55 0110111 1b8000?1bffff sa56 0 1 1 1 0 0 0 1c0000?1c7fff sa57 0 1 1 1 0 0 1 1c8000?1cffff sa58 0 1 1 1 0 1 0 1d0000?1d7fff sa59 0 1 1 1 0 1 1 1d8000?1dffff sa60 0111100 1e0000?1e7fff sa61 0111101 1e8000?1effff sa62 0111110 1f0000?1f7fff sa63 0111111 1f8000?1fffff sa96 1 1 0 0 0 0 0 300000?307fff sa97 1 1 0000 1 308000?30ffff sa98 1 1 0 0 0 1 0 310000?317fff sa99 1 1 000 1 1 318000?31ffff sa100 1 1 0 0 1 0 0 320000?327fff sa101 1 1 0 0 1 0 1 328000?32ffff sa102 1 1 0 0 1 1 0 330000?337fff sa103 1100111 338000?33ffff sa104 1 1 0 1 0 0 0 340000?347fff sa105 1 101001 348000?34ffff sa106 1 1 0 1 0 1 0 350000?357fff sa107 1 10101 1 358000?35ffff sa108 1 1 0 1 1 0 0 360000?367fff table 10. s29gl064m (model r5) sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal)
56 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa109 1 1 0 1 1 0 1 368000?36ffff sa110 1 1 0 1 1 1 0 370000?377fff sa111 1101111 378000?37ffff sa112 1 1 1 0 0 0 0 380000?387fff sa113 1 1 1 0 0 0 1 388000?38ffff sa114 1 1 1 0 0 1 0 390000?397fff sa115 1 1 1 0 0 1 1 398000?39ffff sa116 1 1 1 0 1 0 0 3a0000?3a7fff sa117 1 1 1 0 1 0 1 3a8000?3affff sa118 1 1 1 0 1 1 0 3b0000?3b7fff sa119 1 1 1 0 1 1 1 3b8000?3bffff sa120 1 1 1 1 0 0 0 3c0000?3c7fff sa121 1111001 3c8000?3cffff sa122 1 1 1 1 0 1 0 3d0000?3d7fff sa123 1111011 3d8000?3dffff sa124 1111100 3e0000?3e7fff sa125 1111101 3e8000?3effff sa126 1111110 3f0000?3f7fff sa127 1111111 3f8000?3fffff table 11. s29gl064m (models r6, r7) sector address table sector a21?a15 16-bit address range (in hexadecimal) sa0 0 0 0 0 0 0 0 000000?007fff sa1 0 0 0 0 0 0 1 008000?00ffff sa2 0 0 0 0 0 1 0 010000?017fff sa3 0 0 0 0 0 1 1 018000?01ffff sa4 0 0 0 0 1 0 0 020000?027fff sa5 0 0 0 0 1 0 1 028000?02ffff sa6 0 0 0 0 1 1 0 030000?037fff sa7 0 0 0 0 1 1 1 038000?03ffff sa8 0 0 0 1 0 0 0 040000?047fff sa9 0 0 0 1 0 0 1 048000?04ffff sa10 0 0 0 1 0 1 0 050000?057fff sa11 0 0 0 1 0 1 1 058000?05ffff sa12 0 0 0 1 1 0 0 060000?067fff sa13 0 0 0 1 1 0 1 068000?06ffff sa14 0 0 0 1 1 1 0 070000?077fff sa15 0 0 0 1 1 1 1 078000?07ffff sa16 0 0 1 0 0 0 0 080000?087fff sa17 0 0 1 0 0 0 1 088000?08ffff sa18 0 0 1 0 0 1 0 090000?097fff sa19 0 0 1 0 0 1 1 098000?09ffff sa20 0 0 1 0 1 0 0 0a0000?0a7fff table 10. s29gl064m (model r5) sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 57 preliminary sa21 0 0 1 0 1 0 1 0a8000?0affff sa22 0 0 1 0 1 1 0 0b0000?0b7fff sa23 0 0 1 0 1 1 1 0b8000?0bffff sa24 0 0 1 1 0 0 0 0c0000?0c7fff sa25 0 0 1 1 0 0 1 0c8000?0cffff sa26 0 0 1 1 0 1 0 0d0000?0d7fff sa27 0 0 1 1 0 1 1 0d8000?0dffff sa28 0 0 1 1 1 0 0 0e0000?0e7fff sa29 0 0 1 1 1 0 1 0e8000?0effff sa30 0 0 1 1 1 1 0 0f0000?0f7fff sa31 0 0 1 1 1 1 1 0f8000?0fffff sa64 1 0 0 0 0 0 0 200000?207fff sa65 1 0 0 0 0 0 1 208000?20ffff sa66 1 0 0 0 0 1 0 210000?217fff sa67 1 0 0 0 0 1 1 218000?21ffff sa68 1 0 0 0 1 0 0 220000?227fff sa69 1 0 0 0 1 0 1 228000?22ffff sa70 1 0 0 0 1 1 0 230000?237fff sa71 1 0 0 0 1 1 1 238000?23ffff sa72 1 0 0 1 0 0 0 240000?247fff sa73 1 0 0 1 0 0 1 248000?24ffff sa74 1 0 0 1 0 1 0 250000?257fff sa75 1 0 0 1 0 1 1 258000?25ffff sa76 1 0 0 1 1 0 0 260000?267fff sa77 1 0 0 1 1 0 1 268000?26ffff sa78 1 0 0 1 1 1 0 270000?277fff sa79 1 0 0 1 1 1 1 278000?27ffff sa80 1 0 1 0 0 0 0 280000?287fff sa81 1 0 1 0 0 0 1 288000?28ffff sa82 1 0 1 0 0 1 0 290000?297fff sa83 1 0 1 0 0 1 1 298000?29ffff sa84 1 0 1 0 1 0 0 2a0000?2a7fff sa85 1 0 1 0 1 0 1 2a8000?2affff sa86 1 0 1 0 1 1 0 2b0000?2b7fff sa87 1 0 1 0 1 1 1 2b8000?2bffff sa88 1 0 1 1 0 0 0 2c0000?2c7fff sa89 1 0 1 1 0 0 1 2c8000?2cffff sa90 1 0 1 1 0 1 0 2d0000?2d7fff sa91 1 0 1 1 0 1 1 2d8000?2dffff sa92 1 0 1 1 1 0 0 2e0000?2e7fff sa93 1 0 1 1 1 0 1 2e8000?2effff sa94 1 0 1 1 1 1 0 2f0000?2f7fff sa95 1 0 1 1 1 1 1 2f8000?2fffff sa32 0 1 0 0 0 0 0 100000?107fff sa33 0 1 0 0 0 0 1 108000?10ffff table 11. s29gl064m (models r6, r7) sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal)
58 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa34 0 1 0 0 0 1 0 110000?117fff sa35 0 1 0 0 0 1 1 118000?11ffff sa36 0 1 0 0 1 0 0 120000?127fff sa37 0 1 0 0 1 0 1 128000?12ffff sa38 0 1 0 0 1 1 0 130000?137fff sa39 0 1 0 0 1 1 1 138000?13ffff sa40 0 1 0 1 0 0 0 140000?147fff sa41 0 1 0 1 0 0 1 148000?14ffff sa42 0 1 0 1 0 1 0 150000?157fff sa43 0 1 0 1 0 1 1 158000?15ffff sa44 0 1 0 1 1 0 0 160000?167fff sa45 0 1 0 1 1 0 1 168000?16ffff sa46 0 1 0 1 1 1 0 170000?177fff sa47 0 1 0 1 1 1 1 178000?17ffff sa48 0 1 1 0 0 0 0 180000?187fff sa49 0 1 1 0 0 0 1 188000?18ffff sa50 0 1 1 0 0 1 0 190000?197fff sa51 0 1 1 0 0 1 1 198000?19ffff sa52 0 1 1 0 1 0 0 1a0000?1a7fff sa53 0 1 1 0 1 0 1 1a8000?1affff sa54 0 1 1 0 1 1 0 1b0000?1b7fff sa55 0 1 1 0 1 1 1 1b8000?1bffff sa56 0 1 1 1 0 0 0 1c0000?1c7fff sa57 0 1 1 1 0 0 1 1c8000?1cffff sa58 0 1 1 1 0 1 0 1d0000?1d7fff sa59 0 1 1 1 0 1 1 1d8000?1dffff sa60 0 1 1 1 1 0 0 1e0000?1e7fff sa61 0 1 1 1 1 0 1 1e8000?1effff sa62 0 1 1 1 1 1 0 1f0000?1f7fff sa63 0 1 1 1 1 1 1 1 f8000?1 fffff sa96 1 1 0 0 0 0 0 300000?307fff sa97 1 1 0 0 0 0 1 308000?30ffff sa98 1 1 0 0 0 1 0 310000?317fff sa99 1 1 0 0 0 1 1 318000?31ffff sa100 1 1 0 0 1 0 0 320000?327fff sa101 1 1 0 0 1 0 1 328000?32ffff sa102 1 1 0 0 1 1 0 330000?337fff sa103 1 1 0 0 1 1 1 338000?33ffff sa104 1 1 0 1 0 0 0 340000?347fff sa105 1 1 0 1 0 0 1 348000?34ffff sa106 1 1 0 1 0 1 0 350000?357fff sa107 1 1 0 1 0 1 1 358000?35ffff sa108 1 1 0 1 1 0 0 360000?367fff sa109 1 1 0 1 1 0 1 368000?36ffff sa110 1 1 0 1 1 1 0 370000?377fff table 11. s29gl064m (models r6, r7) sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 59 preliminary sa111 1 1 0 1 1 1 1 378000?37ffff sa112 1 1 1 0 0 0 0 380000?387fff sa113 1 1 1 0 0 0 1 388000?38ffff sa114 1 1 1 0 0 1 0 390000?397fff sa115 1 1 1 0 0 1 1 398000?39ffff sa116 1 1 1 0 1 0 0 3a0000?3a7fff sa117 1 1 1 0 1 0 1 3a8000?3affff sa118 1 1 1 0 1 1 0 3b0000?3b7fff sa119 1 1 1 0 1 1 1 3b8000?3bffff sa120 1 1 1 1 0 0 0 3c0000?3c7fff sa121 1 1 1 1 0 0 1 3c8000?3cffff sa122 1 1 1 1 0 1 0 3d0000?3d7fff sa123 1 1 1 1 0 1 1 3d8000?3dffff sa124 1 1 1 1 1 0 0 3e0000?3e7fff sa125 1 1 1 1 1 0 1 3e8000?3effff sa126 1 1 1 1 1 1 0 3f0000?3f7fff sa127 1 1 1 1 1 1 1 3f8000?3fffff table 11. s29gl064m (models r6, r7) sector address table (continued) sector a21?a15 16-bit address range (in hexadecimal)
60 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 12. s29gl128m sector address table sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 00000000 64/32 000 000?00ffff 000000?007fff sa1 0000000 1 64/32 010 000?01ffff 008000?00ffff sa2 000000 1 0 64/32 020 000?02ffff 010000?017fff sa3 000000 1 1 64/32 030 000?03ffff 018000?01ffff sa4 00000 1 00 64/32 040 000?04ffff 020000?027fff sa5 00000 1 0 1 64/32 050 000?05ffff 028000?02ffff sa6 00000 1 1 0 64/32 060 000?06ffff 030000?037fff sa7 00000 1 1 1 64/32 070 000?07ffff 038000?03ffff sa8 0000 1 000 64/32 080 000?08ffff 040000?047fff sa9 0000 1 00 1 64/32 090 000?09ffff 048000?04ffff sa10 0000 1 0 1 0 64/32 0a0 000?0affff 050000?057fff sa11 0000 1 0 1 1 64/32 0b0 000?0bffff 05 8000?05ffff sa12 0000 1 1 00 64/32 0c0 000?0cffff 060000?067fff sa13 0000 1 1 0 1 64/32 0d0 000?0dffff 068000?06ffff sa14 0000 1 1 1 0 64/32 0e0 000?0effff 070000?077fff sa15 0000 1111 64/32 0f0 000?0 fffff 078000 ?07ffff sa16 0 0 0 1 0 0 0 0 64/32 100000?10ffff 080000?087fff sa17 0 0 0 1 0 0 0 1 64/32 110000?11ffff 088000?08ffff sa18 0 0 0 1 0 0 1 0 64/32 12 0000?12 ffff 090000?097fff sa19 0 0 0 1 0 0 1 1 64/32 130000?13ffff 098000?09ffff sa20 0 0 0 1 0 1 0 0 64/32 140000?14ffff 0a0000?0a7fff sa21 0 0 0 1 0 1 0 1 64/32 150000?15ffff 0a8000?0affff sa22 0 0 0 1 0 1 1 0 64/32 160000?16ffff 0b0000?0b7fff sa23 0 0 0 1 0 1 1 1 64/32 170000?17ffff 0b8000?0bffff sa24 0 0 0 1 1 0 0 0 64/32 180000?18ffff 0c0000?0c7fff sa25 0 0 0 1 1 0 0 1 64/32 190000?19ffff 0c8000?0cffff sa26 0 0 0 1 1 0 1 0 64/32 1a0000?1affff 0d0000?0d7fff sa27 0 0 0 1 1 0 1 1 64/32 1b0000?1bffff 0d8000?0dffff sa28 0 0 0 1 1 1 0 0 64/32 1c0000?1cffff 0e0000?0e7fff sa29 0 0 0 1 1 1 0 1 64/32 1d0000?1dffff 0e8000?0effff sa30 00011110 64/32 1e0 000?1effff 0f0000?0f7fff sa31 00011111 64/32 1f0 000?1fffff 0f8000?0fffff sa32 0 0 1 0 0 0 0 0 64/32 200000?20ffff 100000?107fff sa33 0 0 1 0 0 0 0 1 64/32 210 000?21ffff 108000?10ffff sa34 0 0 1 0 0 0 1 0 64/32 220000?22ffff 110000?117fff sa35 0 0 1 0 0 0 1 1 64/32 230000?23ffff 118000?11ffff sa36 0 0 1 0 0 1 0 0 64/32 240000?24ffff 120000?127fff sa37 0 0 1 0 0 1 0 1 64/32 250000?25ffff 128000?12ffff sa38 0 0 1 0 0 1 1 0 64/32 260000?26ffff 130000?137fff sa39 0 0 1 0 0 1 1 1 64/32 270000?27ffff 138000?13ffff sa40 0 0 1 0 1 0 0 0 64/32 280000?28ffff 140000?147fff sa41 0 0 1 0 1 0 0 1 64/32 290000?29ffff 148000?14ffff sa42 0 0 1 0 1 0 1 0 64/32 2 a0000?2a ffff 150000 ?157fff sa43 0 0 1 0 1 0 1 1 64/32 2b0000?2bffff 158000?15ffff sa44 0 0 1 0 1 1 0 0 64/32 2c0000?2cffff 160000?167fff
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 61 preliminary sa45 0 0 1 0 1 1 0 1 64/32 2d0000?2dffff 168000?16ffff sa46 0 0 1 0 1 1 1 0 64/32 2e0000?2effff 170000?177fff sa47 00101111 64/32 2f0 000?2fffff 178000?17ffff sa48 0 0 1 1 0 0 0 0 64/32 300000?30ffff 180000?187fff sa49 0 0 1 1 0 0 0 1 64/32 310000?31ffff 188000?18ffff sa50 0 0 1 1 0 0 1 0 64/32 320000?32ffff 190000?197fff sa51 0 0 1 1 0 0 1 1 64/32 330000?33ffff 198000?19ffff sa52 0 0 1 1 0 1 0 0 64/32 340000?34ffff 1a0000?1a7fff sa53 0 0 1 1 0 1 0 1 64/32 350000?35ffff 1a8000?1affff sa54 0 0 1 1 0 1 1 0 64/32 360000?36ffff 1b0000?1b7fff sa55 0 0 1 1 0 1 1 1 64/32 370000?37ffff 1b8000?1bffff sa56 0 0 1 1 1 0 0 0 64/32 380000?38ffff 1c0000?1c7fff sa57 0 0 1 1 1 0 0 1 64/32 390 000?39 ffff 1c8000 ?1cffff sa58 0 0 1 1 1 0 1 0 64/32 3a0000?3affff 1d0000?1d7fff sa59 0 0 1 1 1 0 1 1 64/32 3b0000?3bffff 1d8000?1dffff sa60 00111100 64/32 3c0 000?3cffff 1e0000?1e7fff sa61 00111101 64/32 3d0 000?3dffff 1e8000?1effff sa62 00111110 64/32 3e0 000?3effff 1f0000?1f7fff sa63 00111111 64/32 3f0 000?3fffff 1f8000?1fffff sa64 0 1 0 0 0 0 0 0 64/32 400000?40ffff 200000?207fff sa65 0 1 0 0 0 0 0 1 64/32 410000?41ffff 208000?20ffff sa66 0 1 0 0 0 0 1 0 64/32 420000?42ffff 210000?217fff sa67 0 1 0 0 0 0 1 1 64/32 430000?43ffff 218000?21ffff sa68 0 1 0 0 0 1 0 0 64/32 440000?44ffff 220000?227fff sa69 0 1 0 0 0 1 0 1 64/32 450000?45ffff 228000?22ffff sa70 0 1 0 0 0 1 1 0 64/32 460000?46ffff 230000?237fff sa71 0 1 0 0 0 1 1 1 64/32 470000?47ffff 238000?23ffff sa72 0 1 0 0 1 0 0 0 64/32 480 000?48 ffff 24 0000?247fff sa73 0 1 0 0 1 0 0 1 64/32 490000?49ffff 248000?24ffff sa74 0 1 0 0 1 0 1 0 64/32 4a0000?4affff 250000?257fff sa75 0 1 0 0 1 0 1 1 64/32 4b0000?4bffff 258000?25ffff sa76 0 1 0 0 1 1 0 0 64/32 4c0000?4cffff 260000?267fff sa77 0 1 0 0 1 1 0 1 64/32 4d0000?4dffff 268000?26ffff sa78 0 1 0 0 1 1 1 0 64/32 4e0000?4effff 270000?277fff sa79 01001111 64/32 4f0 000?4fffff 278000?27ffff sa80 0 1 0 1 0 0 0 0 64/32 500000?50ffff 280000?287fff sa81 0 1 0 1 0 0 0 1 64/32 510000?51ffff 288000?28ffff sa82 0 1 0 1 0 0 1 0 64/32 520000?52ffff 290000?297fff sa83 0 1 0 1 0 0 1 1 64/32 530000?53ffff 298000?29ffff sa84 0 1 0 1 0 1 0 0 64/32 540000?54ffff 2a0000?2a7fff sa85 0 1 0 1 0 1 0 1 64/32 550000?55ffff 2a8000?2affff sa86 0 1 0 1 0 1 1 0 64/32 560000?56ffff 2b0000?2b7fff sa87 0 1 0 1 0 1 1 1 64/32 570000?57ffff 2b8000?2bffff sa88 0 1 0 1 1 0 0 0 64/32 580000?58ffff 2c0000?2c7fff sa89 0 1 0 1 1 0 0 1 64/32 590000?59ffff 2c8000?2cffff table 12. s29gl128m sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
62 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa90 0 1 0 1 1 0 1 0 64/32 5a0000?5affff 2d0000?2d7fff sa91 0 1 0 1 1 0 1 1 64/32 5b0000?5bffff 2d8000?2dffff sa92 0 1 0 1 1 1 0 0 64/32 5c0000?5cffff 2e0000?2e7fff sa93 0 1 0 1 1 1 0 1 64/32 5d0000?5dffff 2e8000?2effff sa94 01011110 64/32 5e0 000?5effff 2f0000?2f7fff sa95 01011111 64/32 5f0 000?5ff fff 2f8000 ?2fffff sa96 0 1 1 0 0 0 0 0 64/32 600000?60ffff 300000?307fff sa97 0 1 1 0 0 0 0 1 64/32 610000?61ffff 308000?30ffff sa98 0 1 1 0 0 0 1 0 64/32 620000?62ffff 310000?317fff sa99 0 1 1 0 0 0 1 1 64/32 630000?63ffff 318000?31ffff sa100 0 1 1 0 0 1 0 0 64/32 640000?64ffff 320000?327fff sa101 0 1 1 0 0 1 0 1 64/32 650000?65ffff 328000?32ffff sa102 0 1 1 0 0 1 1 0 64/32 660000?66ffff 330000?337fff sa103 0 1 1 0 0 1 1 1 64/32 670000?67ffff 338000?33ffff sa104 0 1 1 0 1 0 0 0 64/32 680000?68ffff 340000?347fff sa105 0 1 1 0 1 0 0 1 64/32 690000?69ffff 348000?34ffff sa106 0 1 1 0 1 0 1 0 64/32 6a0000?6affff 350000?357fff sa107 0 1 1 0 1 0 1 1 64/32 6b0000?6bffff 358000?35ffff sa108 0 1 1 0 1 1 0 0 64/32 6c0000?6cffff 360000?367fff sa109 0 1 1 0 1 1 0 1 64/32 6d0000?6dffff 368000?36ffff sa110 0 1 1 0 1 1 1 0 64/32 6e0000?6effff 370000?377fff sa111 01101111 64/32 6f0 000?6fffff 378000?37ffff sa112 0 1 1 1 0 0 0 0 64/32 700000?70ffff 380000?387fff sa113 0 1 1 1 0 0 0 1 64/32 710000?71ffff 388000?38ffff sa114 0 1 1 1 0 0 1 0 64/32 720000?72ffff 390000?397fff sa115 0 1 1 1 0 0 1 1 64/32 730000?73ffff 398000?39ffff sa116 0 1 1 1 0 1 0 0 64/32 740000?74ffff 3a0000?3a7fff sa117 0 1 1 1 0 1 0 1 64/32 750000?75ffff 3a8000?3affff sa118 0 1 1 1 0 1 1 0 64/32 760000?76ffff 3b0000?3b7fff sa119 0 1 1 1 0 1 1 1 64/32 770000?77ffff 3b8000?3bffff sa120 0 1 1 1 1 0 0 0 64/32 780000?78ffff 3c0000?3c7fff sa121 0 1 1 1 1 0 0 1 64/32 790000?79ffff 3c8000?3cffff sa122 0 1 1 1 1 0 1 0 64/32 7a0000?7affff 3d0000?3d7fff sa123 0 1 1 1 1 0 1 1 64/32 7b 0000?7bffff 3 d8000?3dffff sa124 01111100 64/32 7c0 000?7cffff 3e0000?3e7fff sa125 01111101 64/32 7d0 000?7dffff 3e8000?3effff sa126 01111110 64/32 7e0 000?7effff 3f0000?3f7fff sa127 01111111 64/32 7f0 000?7fffff 3f8000?3fffff sa128 1 0000000 64/32 800 000?80ffff 400000?407fff sa129 1 000000 1 64/32 810 000?81ffff 408000?40ffff sa130 1 00000 1 0 64/32 820 000?82ffff 410000?417fff sa131 1 00000 1 1 64/32 830 000?83ffff 418000?41ffff sa132 1 0000 1 00 64/32 840 000?84 ffff 420000 ?427fff sa133 1 0000 1 0 1 64/32 850 000?85ffff 428000?42ffff sa134 1 0000 1 1 0 64/32 860 000?86ffff 430000?437fff table 12. s29gl128m sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 63 preliminary sa135 1 0000 1 1 1 64/32 870 000?87ffff 438000?43ffff sa136 1 0 0 0 1 0 0 0 64/32 880000?88ffff 440000?447fff sa137 1 0 0 0 1 0 0 1 64/32 890000?89ffff 448000?44ffff sa138 1 0 0 0 1 0 1 0 64/32 8a0000?8affff 450000?457fff sa139 1 0 0 0 1 0 1 1 64/32 8b0000?8bffff 458000?45ffff sa140 1 0 0 0 1 1 0 0 64/32 8c0000?8cffff 460000?467fff sa141 1 0 0 0 1 1 0 1 64/32 8d0000?8dffff 468000?46ffff sa142 1 0 0 0 1 1 1 0 64/32 8e0000?8effff 470000?477fff sa143 10001111 64/32 8f0 000?8fffff 478000?47ffff sa144 1 0 0 1 0 0 0 0 64/32 900000?90ffff 480000?487fff sa145 1 0 0 1 0 0 0 1 64/32 910000?91ffff 488000?48ffff sa146 1 0 0 1 0 0 1 0 64/32 920000?92ffff 490000?497fff sa147 1 0 0 1 0 0 1 1 64/32 930 000?93 ffff 498000 ?49ffff sa148 1 0 0 1 0 1 0 0 64/32 940000?94ffff 4a0000?4a7fff sa149 1 0 0 1 0 1 0 1 64/32 950000?95ffff 4a8000?4affff sa150 1 0 0 1 0 1 1 0 64/32 960000?96ffff 4b0000?4b7fff sa151 1 0 0 1 0 1 1 1 64/32 970000?97ffff 4b8000?4bffff sa152 1 0 0 1 1 0 0 0 64/32 980000?98ffff 4c0000?4c7fff sa153 1 0 0 1 1 0 0 1 64/32 990000?99ffff 4c8000?4cffff sa154 1 0 0 1 1 0 1 0 64/32 9a0000?9affff 4d0000?4d7fff sa155 1 0 0 1 1 0 1 1 64/32 9b0000?9bffff 4d8000?4dffff sa156 1 0 0 1 1 1 0 0 64/32 9c0 000?9c ffff 4e0000 ?4e7fff sa157 1 0 0 1 1 1 0 1 64/32 9d0000?9dffff 4e8000?4effff sa158 10011110 64/32 9e0 000?9effff 4f0000?4f7fff sa159 10011111 64/32 9f0 000?9fffff 4f8000?4fffff sa160 1 0 1 0 0 0 0 0 64/32 a00000?a0ffff 500000?507fff sa161 1 0 1 0 0 0 0 1 64/32 a10 000?a1ffff 50 8000?50ffff sa162 1 0 1 0 0 0 1 0 64/32 a2 0000?a2 ffff 510000 ?517fff sa163 1 0 1 0 0 0 1 1 64/32 a30000?a3ffff 518000?51ffff sa164 1 0 1 0 0 1 0 0 64/32 a40000?a4ffff 520000?527fff sa165 1 0 1 0 0 1 0 1 64/32 a50000?a5ffff 528000?52ffff sa166 1 0 1 0 0 1 1 0 64/32 a60000?a6ffff 530000?537fff sa167 1 0 1 0 0 1 1 1 64/32 a70000?a7ffff 538000?53ffff sa168 1 0 1 0 1 0 0 0 64/32 a80000?a8ffff 540000?547fff sa169 1 0 1 0 1 0 0 1 64/32 a90000?a9ffff 548000?54ffff sa170 1 0 1 0 1 0 1 0 64/32 aa0000?aaffff 550000?557fff sa171 1 0 1 0 1 0 1 1 64/32 ab0000?abffff 558000?55ffff sa172 1 0 1 0 1 1 0 0 64/32 ac 0000?ac ffff 56 0000?567fff sa173 1 0 1 0 1 1 0 1 64/32 ad0000?adffff 568000?56ffff sa174 1 0 1 0 1 1 1 0 64/32 ae0000?aeffff 570000?577fff sa175 10101111 64/32 af0 000?afffff 578000?57ffff sa176 1 0 1 1 0 0 0 0 64/32 b00000?b0ffff 580000?587fff sa177 1 0 1 1 0 0 0 1 64/32 b10000?b1ffff 588000?58ffff sa178 1 0 1 1 0 0 1 0 64/32 b20000?b2ffff 590000?597fff sa179 1 0 1 1 0 0 1 1 64/32 b30000?b3ffff 598000?59ffff table 12. s29gl128m sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
64 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa180 1 0 1 1 0 1 0 0 64/32 b40000?b4ffff 5a0000?5a7fff sa181 1 0 1 1 0 1 0 1 64/32 b50000?b5ffff 5a8000?5affff sa182 1 0 1 1 0 1 1 0 64/32 b60000?b6ffff 5b0000?5b7fff sa183 1 0 1 1 0 1 1 1 64/32 b70 000?b7ffff 5b8000?5bffff sa184 1 0 1 1 1 0 0 0 64/32 b80000?b8ffff 5c0000?5c7fff sa185 1 0 1 1 1 0 0 1 64/32 b90000?b9ffff 5c8000?5cffff sa186 1 0 1 1 1 0 1 0 64/32 ba0000?baffff 5d0000?5d7fff sa187 1 0 1 1 1 0 1 1 64/32 bb0000?bbffff 5d8000?5dffff sa188 10111100 64/32 bc0 000?bcffff 5e0000?5e7fff sa189 10111101 64/32 bd0 000?bdffff 5e8000?5effff sa190 10111110 64/32 be0 000?beffff 5f0000?5f7fff sa191 10111111 64/32 bf0 000?bfffff 5f8000?5fffff sa192 1 1 0 0 0 0 0 0 64/32 c00000?c0ffff 600000?607fff sa193 1 1 0 0 0 0 0 1 64/32 c10000?c1ffff 608000?60ffff sa194 1 1 0 0 0 0 1 0 64/32 c20000?c2ffff 610000?617fff sa195 1 1 0 0 0 0 1 1 64/32 c30000?c3ffff 618000?61ffff sa196 1 1 0 0 0 1 0 0 64/32 c40000?c4ffff 620000?627fff sa197 1 1 0 0 0 1 0 1 64/32 c50000?c5ffff 628000?62ffff sa198 1 1 0 0 0 1 1 0 64/32 c60000?c6ffff 630000?637fff sa199 1 1 0 0 0 1 1 1 64/32 c70000?c7ffff 638000?63ffff sa200 1 1 0 0 1 0 0 0 64/32 c80000?c8ffff 640000?647fff sa201 1 1 0 0 1 0 0 1 64/32 c9 0000?c9 ffff 648 000?64ffff sa202 1 1 0 0 1 0 1 0 64/32 ca0000?caffff 650000?657fff sa203 1 1 0 0 1 0 1 1 64/32 cb0000?cbffff 658000?65ffff sa204 1 1 0 0 1 1 0 0 64/32 cc0000?ccffff 660000?667fff sa205 1 1 0 0 1 1 0 1 64/32 cd0000?cdffff 668000?66ffff sa206 1 1 0 0 1 1 1 0 64/32 ce0000?ceffff 670000?677fff sa207 11001111 64/32 cf0 000?cfffff 678000?67ffff sa208 1 1 0 1 0 0 0 0 64/32 d00000?d0ffff 680000?687fff sa209 1 1 0 1 0 0 0 1 64/32 d10000?d1ffff 688000?68ffff sa210 1 1 0 1 0 0 1 0 64/32 d20000?d2ffff 690000?697fff sa211 1 1 0 1 0 0 1 1 64/32 d30000?d3ffff 698000?69ffff sa212 1 1 0 1 0 1 0 0 64/32 d40000?d4ffff 6a0000?6a7fff sa213 1 1 0 1 0 1 0 1 64/32 d50000?d5ffff 6a8000?6affff sa214 1 1 0 1 0 1 1 0 64/32 d60000?d6ffff 6b0000?6b7fff sa215 1 1 0 1 0 1 1 1 64/32 d70000?d7ffff 6b8000?6bffff sa216 1 1 0 1 1 0 0 0 64/32 d80000?d8ffff 6c0000?6c7fff sa217 1 1 0 1 1 0 0 1 64/32 d90000?d9ffff 6c8000?6cffff sa218 1 1 0 1 1 0 1 0 64/32 da0000?daffff 6d0000?6d7fff sa219 1 1 0 1 1 0 1 1 64/32 db0000?dbffff 6d8000?6dffff sa220 1 1 0 1 1 1 0 0 64/32 dc0000?dcffff 6e0000?6e7fff sa221 1 1 0 1 1 1 0 1 64/32 dd0000?ddffff 6e8000?6effff sa222 11011110 64/32 de0 000?deffff 6f0000?6f7fff sa223 11011111 64/32 df0 000?dfffff 6f8000?6fffff sa224 1 1 1 0 0 0 0 0 64/32 e00000?e0ffff 700000?707fff table 12. s29gl128m sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 65 preliminary sa225 1 1 1 0 0 0 0 1 64/32 e10000?e1ffff 708000?70ffff sa226 1 1 1 0 0 0 1 0 64/32 e20000?e2ffff 710000?717fff sa227 1 1 1 0 0 0 1 1 64/32 e30000?e3ffff 718000?71ffff sa228 1 1 1 0 0 1 0 0 64/32 e40000?e4ffff 720000?727fff sa229 1 1 1 0 0 1 0 1 64/32 e50000?e5ffff 728000?72ffff sa230 1 1 1 0 0 1 1 0 64/32 e60000?e6ffff 730000?737fff sa231 1 1 1 0 0 1 1 1 64/32 e70000?e7ffff 738000?73ffff sa232 1 1 1 0 1 0 0 0 64/32 e80000?e8ffff 740000?747fff sa233 1 1 1 0 1 0 0 1 64/32 e90000?e9ffff 748000?74ffff sa234 1 1 1 0 1 0 1 0 64/32 ea0000?eaffff 750000?757fff sa235 1 1 1 0 1 0 1 1 64/32 eb0000?ebffff 758000?75ffff sa236 1 1 1 0 1 1 0 0 64/32 ec0000?ecffff 760000?767fff sa237 1 1 1 0 1 1 0 1 64/32 ed0000?edffff 768000?76ffff sa238 1 1 1 0 1 1 1 0 64/32 ee0000?eeffff 770000?777fff sa239 11101111 64/32 ef0 000?efffff 778000?77ffff sa240 1 1 1 1 0 0 0 0 64/32 f00000?f0ffff 780000?787fff sa241 1 1 1 1 0 0 0 1 64/32 f10000?f1ffff 788000?78ffff sa242 1 1 1 1 0 0 1 0 64/32 f20000?f2ffff 790000?797fff sa243 1 1 1 1 0 0 1 1 64/32 f30000?f3ffff 798000?79ffff sa244 1 1 1 1 0 1 0 0 64/32 f40000?f4ffff 7a0000?7a7fff sa245 1 1 1 1 0 1 0 1 64/32 f50000?f5ffff 7a8000?7affff sa246 1 1 1 1 0 1 1 0 64/32 f60000?f6ffff 7b0000?7b7fff sa247 1 1 1 1 0 1 1 1 64/32 f70 000?f7f fff 7b8000?7bffff sa248 1 1 1 1 1 0 0 0 64/32 f80000?f8ffff 7c0000?7c7fff sa249 1 1 1 1 1 0 0 1 64/32 f90000?f9ffff 7c8000?7cffff sa250 1 1 1 1 1 0 1 0 64/32 fa0000?faffff 7d0000?7d7fff sa251 1 1 1 1 1 0 1 1 64/32 fb0000?fbffff 7d8000?7dffff sa252 11111100 64/32 fc0 000?fcffff 7e0000?7e7fff sa253 11111101 64/32 fd0 000?fdffff 7e8000?7effff sa254 11111110 64/32 fe0 000?feffff 7f0000?7f7fff sa255 11111111 64/32 ff0 000?ffffff 7f8000?7fffff table 12. s29gl128m sector address table (continued) sector a22?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
66 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 13. s29gl256m sector address table sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal) sa0 000000000 64/32 00 00000?000ffff 000000?007fff sa1 00000000 1 64/32 0010000?001ffff 008000?00 ffff sa2 0000000 1 0 64/32 0020000?002ffff 010 000?017fff sa3 0000000 1 1 64/32 0030000?003ffff 018000?01ffff sa4 000000 1 00 64/32 0040000?004ffff 020 000?027fff sa5 000000 1 0 1 64/32 0050000?005ffff 028000?02ffff sa6 000000 1 1 0 64/32 0060000?006ffff 030 000?037fff sa7 000000 1 1 1 64/32 0070000?007ffff 038000?03ffff sa8 00000 1 000 64/32 0080000?008ffff 040 000?047fff sa9 00000 1 00 1 64/32 0090000?009ffff 048000?04ffff sa10 00000 1 0 1 0 64/32 00a0000?00affff 050 000?057fff sa11 00000 1 0 1 1 64/32 00b0000?00b ffff 058000?05ffff sa12 00000 1 1 00 64/32 00c0000?00cffff 060 000?067fff sa13 00000 1 1 0 1 64/32 00d0000?00dffff 068000?06ffff sa14 00000 1 1 1 0 64/32 00e0000?00effff 070 000?077fff sa15 00000 1111 64/32 00f0000?00fffff 078000?07ffff sa16 0000 1 0000 64/32 01 00000?010ffff 080000?087fff sa17 0000 1 000 1 64/32 0110000?011ffff 088000?08ffff sa18 0000 1 00 1 0 64/32 0120000?012ffff 090 000?097fff sa19 0000 1 00 1 1 64/32 0130000?013ffff 098000?09ffff sa20 0000 1 0 1 00 64/32 0140000?014ffff 0a0 000?0a7fff sa21 0000 1 0 1 0 1 64/32 0150000?015ffff 0a8000?0affff sa22 0000 1 0 1 1 0 64/32 0160000?016ffff 0b0 000?0b7fff sa23 0000 1 0 1 1 1 64/32 0170000?017ffff 0b8000?0bffff sa24 0000 1 1 000 64/32 0180000?018ffff 0c0 000?0c7fff sa25 0000 1 1 00 1 64/32 0190000?019ffff 0c8000?0cffff sa26 0000 1 1 0 1 0 64/32 01a0000?01affff 0d0 000?0d7fff sa27 0000 1 1 0 1 1 64/32 01b0000?01bffff 0d8000?0dffff sa28 0000 1 1 1 00 64/32 01c0000?01cffff 0e0 000?0e7fff sa29 0000 1 1 1 0 1 64/32 01d0000?01dffff 0e8000?0effff sa30 0000 11110 64/32 01e0000?01effff 0f0 000?0f7fff sa31 0000 11111 64/32 01f0000?01fffff 0f8000?0fffff sa32 000 1 00000 64/32 02 00000?020ffff 100000?107fff sa33 000 1 0000 1 64/32 0210000?021ffff 108000?10ffff sa34 0 0 0 1 0 0 0 1 0 64/32 0220000?022ffff 110000?117fff sa35 0 0 0 1 0 0 0 1 1 64/32 0230000?023ffff 118000?11ffff sa36 0 0 0 1 0 0 1 0 0 64/32 0240000?024ffff 120000?127fff sa37 0 0 0 1 0 0 1 0 1 64/32 0250000?025ffff 128000?12ffff sa38 0 0 0 1 0 0 1 1 0 64/32 0260000?026ffff 130000?137fff sa39 0 0 0 1 0 0 1 1 1 64/32 0270000?027ffff 138000?13ffff sa40 0 0 0 1 0 1 0 0 0 64/32 0280000?028ffff 140000?147fff sa41 0 0 0 1 0 1 0 0 1 64/32 0290000?029ffff 148000?14ffff sa42 0 0 0 1 0 1 0 1 0 64/32 02a0000?02affff 150000?157fff sa43 0 0 0 1 0 1 0 1 1 64/32 02b0000?02bffff 158000?15ffff sa44 0 0 0 1 0 1 1 0 0 64/32 02c0000?02cffff 160000?167fff
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 67 preliminary sa45 0 0 0 1 0 1 1 0 1 64/32 02d0000?02dffff 168000?16ffff sa46 0 0 0 1 0 1 1 1 0 64/32 02e0000?02effff 170000?177fff sa47 000101111 64/32 02f0000?02fffff 178000?17ffff sa48 000 1 1 0000 64/32 03 00000?030ffff 180000?187fff sa49 0 0 0 1 1 0 0 0 1 64/32 0310000?031ffff 188000?18ffff sa50 0 0 0 1 1 0 0 1 0 64/32 0320000?032ffff 190000?197fff sa51 0 0 0 1 1 0 0 1 1 64/32 0330000?033ffff 198000?19ffff sa52 0 0 0 1 1 0 1 0 0 64/32 0340000?034ffff 1a0000?1a7fff sa53 0 0 0 1 1 0 1 0 1 64/32 0350000?035ffff 1a8000?1affff sa54 0 0 0 1 1 0 1 1 0 64/32 0360000?036ffff 1b0000?1b7fff sa55 0 0 0 1 1 0 1 1 1 64/32 0370000?037ffff 1b8000?1bffff sa56 0 0 0 1 1 1 0 0 0 64/32 0380000?038ffff 1c0000?1c7fff sa57 0 0 0 1 1 1 0 0 1 64/32 0390000?039ffff 1c8000?1cffff sa58 0 0 0 1 1 1 0 1 0 64/32 03a0000?03affff 1d0000?1d7fff sa59 0 0 0 1 1 1 0 1 1 64/32 03b0000?03bffff 1d8000?1dffff sa60 000111100 64/32 03c0000?03cffff 1e0 000?1e7fff sa61 000111101 64/32 03d0000?03dffff 1e8000?1effff sa62 000111110 64/32 03e0000?03effff 1f0 000?1f7fff sa63 000111111 64/32 03f0000?03f ffff 1f8000?1fffff sa64 00 1 000000 64/32 04 00000?040ffff 200000?207fff sa65 00 1 00000 1 64/32 0410000?041ffff 208000?20ffff sa66 00 1 0000 1 0 64/32 0420000?042ffff 210 000?217fff sa67 00 1 0000 1 1 64/32 0430000?043ffff 218000?21ffff sa68 0 0 1 0 0 0 1 0 0 64/32 0440000?044ffff 220000?227fff sa69 0 0 1 0 0 0 1 0 1 64/32 0450000?045ffff 228000?22ffff sa70 0 0 1 0 0 0 1 1 0 64/32 0460000?046ffff 230000?237fff sa71 0 0 1 0 0 0 1 1 1 64/32 0470000?047ffff 238000?23ffff sa72 0 0 1 0 0 1 0 0 0 64/32 0480000?048ffff 240000?247fff sa73 0 0 1 0 0 1 0 0 1 64/32 0490000?049ffff 248000?24ffff sa74 0 0 1 0 0 1 0 1 0 64/32 04a0000?04affff 250000?257fff sa75 0 0 1 0 0 1 0 1 1 64/32 04b0000?04bffff 258000?25ffff sa76 0 0 1 0 0 1 1 0 0 64/32 04c0000?04cffff 260000?267fff sa77 0 0 1 0 0 1 1 0 1 64/32 04d0000?04dffff 268000?26ffff sa78 0 0 1 0 0 1 1 1 0 64/32 04e0000?04effff 270000?277fff sa79 001001111 64/32 04f0000?04fffff 278000?27ffff sa80 00 1 0 1 0000 64/32 05 00000?050ffff 280000?287fff sa81 0 0 1 0 1 0 0 0 1 64/32 0510000?051ffff 288000?28ffff sa82 0 0 1 0 1 0 0 1 0 64/32 0520000?052ffff 290000?297fff sa83 0 0 1 0 1 0 0 1 1 64/32 0530000?053ffff 298000?29ffff sa84 0 0 1 0 1 0 1 0 0 64/32 0540000?054ffff 2a0000?2a7fff sa85 0 0 1 0 1 0 1 0 1 64/32 0550000?055ffff 2a8000?2affff sa86 0 0 1 0 1 0 1 1 0 64/32 0560000?056ffff 2b0000?2b7fff sa87 0 0 1 0 1 0 1 1 1 64/32 0570000?057ffff 2b8000?2bffff sa88 0 0 1 0 1 1 0 0 0 64/32 0580000?058ffff 2c0000?2c7fff sa89 0 0 1 0 1 1 0 0 1 64/32 0590000?059ffff 2c8000?2cffff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
68 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa90 0 0 1 0 1 1 0 1 0 64/32 05a0000?05affff 2d0000?2d7fff sa91 0 0 1 0 1 1 0 1 1 64/32 05b0000?05bffff 2d8000?2dffff sa92 0 0 1 0 1 1 1 0 0 64/32 05c0000?05cffff 2e0000?2e7fff sa93 0 0 1 0 1 1 1 0 1 64/32 05d0000?05dffff 2e8000?2effff sa94 001011110 64/32 05e0000?05effff 2f0 000?2f7fff sa95 001011111 64/32 05f0000?05fffff 2f8000?2fffff sa96 00 1 1 00000 64/32 06 00000?060ffff 300000?307fff sa97 00 1 1 0000 1 64/32 0610000?061ffff 308000?30ffff sa98 0 0 1 1 0 0 0 1 0 64/32 0620000?062ffff 310000?317fff sa99 0 0 1 1 0 0 0 1 1 64/32 0630000?063ffff 318000?31ffff sa100 0 0 1 1 0 0 1 0 0 64/32 0640000?064ffff 320000?327fff sa101 0 0 1 1 0 0 1 0 1 64/32 0650000?065ffff 328000?32ffff sa102 0 0 1 1 0 0 1 1 0 64/32 0660000?066ffff 330000?337fff sa103 0 0 1 1 0 0 1 1 1 64/32 0670000?067ffff 338000?33ffff sa104 0 0 1 1 0 1 0 0 0 64/32 0680000?068ffff 340000?347fff sa105 0 0 1 1 0 1 0 0 1 64/32 0690000?069ffff 348000?34ffff sa106 0 0 1 1 0 1 0 1 0 64/32 06a0000?06affff 350000?357fff sa107 0 0 1 1 0 1 0 1 1 64/32 06b0000?06bffff 358000?35ffff sa108 0 0 1 1 0 1 1 0 0 64/32 06c 0000?06cffff 36 0000?36 7fff sa109 0 0 1 1 0 1 1 0 1 64/32 06d0000?06dffff 368000?36ffff sa110 0 0 1 1 0 1 1 1 0 64/32 06e0000?06effff 370000?377fff sa111 001101111 64/32 06f0000?06fffff 378000?37ffff sa112 00 1 1 1 0000 64/32 07 00000?070ffff 380000?387fff sa113 0 0 1 1 1 0 0 0 1 64/32 0710000?071ffff 388000?38ffff sa114 0 0 1 1 1 0 0 1 0 64/32 0720000?072ffff 390000?397fff sa115 0 0 1 1 1 0 0 1 1 64/32 0730000?073ffff 398000?39ffff sa116 0 0 1 1 1 0 1 0 0 64/32 0740000?074ffff 3a0000?3a7fff sa117 0 0 1 1 1 0 1 0 1 64/32 0750000?075ffff 3a8000?3affff sa118 0 0 1 1 1 0 1 1 0 64/32 0760000?076ffff 3b0000?3b7fff sa119 0 0 1 1 1 0 1 1 1 64/32 0770000?077ffff 3b8000?3bffff sa120 001111000 64/32 0780000?078ffff 3c0 000?3c7fff sa121 001111001 64/32 0790000?079ffff 3c8000?3c ffff sa122 001111010 64/32 07a0000?07affff 3d0 000?3d7fff sa123 001111011 64/32 07b0000?07bffff 3d8000?3dffff sa124 001111100 64/32 07c0000?07cffff 3e0 000?3e7fff sa125 001111101 64/32 07d0000?07dffff 3e8000?3effff sa126 001111110 64/32 07e0000?07effff 3f0 000?3f7fff sa127 001111111 64/32 07f0000?07fffff 3f8000?3fffff sa128 0 1 0000000 64/32 08 00000?080ffff 400000?407fff sa129 0 1 000000 1 64/32 0810000?081ffff 408000?40ffff sa130 0 1 00000 1 0 64/32 0820000?082ffff 410 000?417fff sa131 0 1 00000 1 1 64/32 0830000?083ffff 418000?41ffff sa132 0 1 0000 1 00 64/32 0840000?084ffff 420 000?427fff sa133 0 1 0000 1 0 1 64/32 0850000?085ffff 428000?42ffff sa134 0 1 0000 1 1 0 64/32 0860000?086ffff 430 000?437fff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 69 preliminary sa135 0 1 0000 1 1 1 64/32 0870000?087ffff 438000?43ffff sa136 0 1 0 0 0 1 0 0 0 64/32 088 0000?088ffff 44 0000?447fff sa137 0 1 0 0 0 1 0 0 1 64/32 0890000?089ffff 448000?44ffff sa138 0 1 0 0 0 1 0 1 0 64/32 08a0000?08affff 450000?457fff sa139 0 1 0 0 0 1 0 1 1 64/32 08b0000?08bffff 458000?45ffff sa140 0 1 0 0 0 1 1 0 0 64/32 08c0000?08cffff 460000?467fff sa141 0 1 0 0 0 1 1 0 1 64/32 08d0000?08dffff 468000?46ffff sa142 0 1 0 0 0 1 1 1 0 64/32 08e0000?08effff 470000?477fff sa143 010001111 64/32 08f0000?08fffff 478000?47ffff sa144 0 1 00 1 0000 64/32 09 00000?090ffff 480000?487fff sa145 0 1 0 0 1 0 0 0 1 64/32 0910000?091ffff 488000?48ffff sa146 0 1 0 0 1 0 0 1 0 64/32 0920000?092ffff 490000?497fff sa147 0 1 0 0 1 0 0 1 1 64/32 0930000?093ffff 498000?49ffff sa148 0 1 0 0 1 0 1 0 0 64/32 0940000?094ffff 4a0000?4a7fff sa149 0 1 0 0 1 0 1 0 1 64/32 0950000?095ffff 4a8000?4affff sa150 0 1 0 0 1 0 1 1 0 64/32 0960000?096ffff 4b0000?4b7fff sa151 0 1 0 0 1 0 1 1 1 64/32 0970000?097ffff 4b8000?4bffff sa152 0 1 0 0 1 1 0 0 0 64/32 0980000?098ffff 4c0000?4c7fff sa153 0 1 0 0 1 1 0 0 1 64/32 0990000?099ffff 4c8000?4cffff sa154 0 1 0 0 1 1 0 1 0 64/32 09a0000?09affff 4d0000?4d7fff sa155 0 1 0 0 1 1 0 1 1 64/32 09b0000?09bffff 4d8000?4dffff sa156 0 1 0 0 1 1 1 0 0 64/32 09c0000?09cffff 4e0000?4e7fff sa157 0 1 0 0 1 1 1 0 1 64/32 09d0000?09dffff 4e8000?4effff sa158 010011110 64/32 09e0000?09effff 4f0 000?4f7fff sa159 010011111 64/32 09f0000?09 fffff 4f8000?4fffff sa160 0 1 0 1 00000 64/32 0a 00000?0a0ffff 500000?507fff sa161 0 1 0 1 0000 1 64/32 0a10000?0a1ffff 508000?50ffff sa162 0 1 0 1 0 0 0 1 0 64/32 0a20000?0a2ffff 510000?517fff sa163 0 1 0 1 0 0 0 1 1 64/32 0a30000?0a3ffff 518000?51ffff sa164 0 1 0 1 0 0 1 0 0 64/32 0a40000?0a4ffff 520000?527fff sa165 0 1 0 1 0 0 1 0 1 64/32 0a50000?0a5ffff 528000?52ffff sa166 0 1 0 1 0 0 1 1 0 64/32 0a60000?0a6ffff 530000?537fff sa167 0 1 0 1 0 0 1 1 1 64/32 0a70000?0a7ffff 538000?53ffff sa168 0 1 0 1 0 1 0 0 0 64/32 0a80000?0a8ffff 540000?547fff sa169 0 1 0 1 0 1 0 0 1 64/32 0a90000?0a9ffff 548000?54ffff sa170 0 1 0 1 0 1 0 1 0 64/32 0aa0000?0aaffff 550000?557fff sa171 0 1 0 1 0 1 0 1 1 64/32 0ab0000?0abffff 558000?55ffff sa172 0 1 0 1 0 1 1 0 0 64/32 0ac0000?0acffff 560000?567fff sa173 0 1 0 1 0 1 1 0 1 64/32 0ad0000?0adffff 568000?56ffff sa174 0 1 0 1 0 1 1 1 0 64/32 0ae0000?0aeffff 570000?577fff sa175 010101111 64/32 0af0000?0afffff 578000?57ffff sa176 0 1 0 1 1 0000 64/32 0b 00000?0b0 ffff 580 000?58 7fff sa177 0 1 0 1 1 0 0 0 1 64/32 0b10000?0b1ffff 588000?58ffff sa178 0 1 0 1 1 0 0 1 0 64/32 0b20000?0b2ffff 590000?597fff sa179 0 1 0 1 1 0 0 1 1 64/32 0b30000?0b3ffff 598000?59ffff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
70 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa180 0 1 0 1 1 0 1 0 0 64/32 0b40000?0b4ffff 5a0000?5a7fff sa181 0 1 0 1 1 0 1 0 1 64/32 0b50000?0b5ffff 5a8000?5affff sa182 0 1 0 1 1 0 1 1 0 64/32 0b60000?0b6ffff 5b0000?5b7fff sa183 0 1 0 1 1 0 1 1 1 64/32 0b70000?0b7ffff 5b8000?5bffff sa184 0 1 0 1 1 1 0 0 0 64/32 0b80000?0b8ffff 5c0000?5c7fff sa185 0 1 0 1 1 1 0 0 1 64/32 0b90000?0b9ffff 5c8000?5cffff sa186 0 1 0 1 1 1 0 1 0 64/32 0ba0000?0baffff 5d0000?5d7fff sa187 0 1 0 1 1 1 0 1 1 64/32 0bb0000?0bbffff 5d8000?5dffff sa188 010111100 64/32 0bc0000?0bcffff 5e0 000?5e7fff sa189 010111101 64/32 0bd0000?0bdffff 5e8000?5effff sa190 010111110 64/32 0be0000?0beffff 5f0 000?5f7fff sa191 010111111 64/32 0bf0000?0bfffff 5f8000?5f ffff sa192 0 1 1 000000 64/32 0c 00000?0c0ffff 600000?607fff sa193 0 1 1 00000 1 64/32 0c10000?0c1ffff 608000?60ffff sa194 0 1 1 0000 1 0 64/32 0c20000?0c2ffff 610 000?617fff sa195 0 1 1 0000 1 1 64/32 0c30000?0c3ffff 618000?61ffff sa196 0 1 1 0 0 0 1 0 0 64/32 0c40000?0c4ffff 620000?627fff sa197 0 1 1 0 0 0 1 0 1 64/32 0c50000?0c5ffff 628000?62ffff sa198 0 1 1 0 0 0 1 1 0 64/32 0c6 0000?0c6 ffff 630000? 637fff sa199 0 1 1 0 0 0 1 1 1 64/32 0c70000?0c7ffff 638000?63ffff sa200 0 1 1 0 0 1 0 0 0 64/32 0c80000?0c8ffff 640000?647fff sa201 0 1 1 0 0 1 0 0 1 64/32 0c90000?0c9ffff 648000?64ffff sa202 0 1 1 0 0 1 0 1 0 64/32 0ca 0000?0ca ffff 650000? 657fff sa203 0 1 1 0 0 1 0 1 1 64/32 0cb0000?0cbffff 658000?65ffff sa204 0 1 1 0 0 1 1 0 0 64/32 0cc0000?0ccffff 660000?667fff sa205 0 1 1 0 0 1 1 0 1 64/32 0cd0000?0cdffff 668000?66ffff sa206 0 1 1 0 0 1 1 1 0 64/32 0ce0000?0ceffff 670000?677fff sa207 011001111 64/32 0cf0000?0cf ffff 678000?67ffff sa208 0 1 1 0 1 0000 64/32 0d 00000?0d0ffff 680000?687fff sa209 0 1 1 0 1 0 0 0 1 64/32 0d10000?0d1ffff 688000?68ffff sa210 0 1 1 0 1 0 0 1 0 64/32 0d2 0000?0d2 ffff 690 000?69 7fff sa211 0 1 1 0 1 0 0 1 1 64/32 0d30000?0d3ffff 698000?69ffff sa212 0 1 1 0 1 0 1 0 0 64/32 0d40000?0d4ffff 6a0000?6a7fff sa213 0 1 1 0 1 0 1 0 1 64/32 0d50000?0d5ffff 6a8000?6affff sa214 0 1 1 0 1 0 1 1 0 64/32 0d60000?0d6ffff 6b0000?6b7fff sa215 0 1 1 0 1 0 1 1 1 64/32 0d70000?0d7ffff 6b8000?6bffff sa216 0 1 1 0 1 1 0 0 0 64/32 0d80000?0d8ffff 6c0000?6c7fff sa217 0 1 1 0 1 1 0 0 1 64/32 0d90000?0d9ffff 6c8000?6cffff sa218 0 1 1 0 1 1 0 1 0 64/32 0da0000?0daffff 6d0000?6d7fff sa219 0 1 1 0 1 1 0 1 1 64/32 0db0000?0dbffff 6d8000?6dffff sa220 0 1 1 0 1 1 1 0 0 64/32 0dc0000?0dcffff 6e0000?6e7fff sa221 0 1 1 0 1 1 1 0 1 64/32 0dd0000?0ddffff 6e8000?6effff sa222 011011110 64/32 0de0000?0deffff 6f0 000?6f7fff sa223 011011111 64/32 0df0000?0dfffff 6f8000?6fffff sa224 0 1 1 1 00000 64/32 0e 00000?0e0ffff 700000?707fff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 71 preliminary sa225 0 1 1 1 0000 1 64/32 0e10000?0e1ffff 708000?70ffff sa226 0 1 1 1 0 0 0 1 0 64/32 0e20000?0e2ffff 710000?717fff sa227 0 1 1 1 0 0 0 1 1 64/32 0e30000?0e3ffff 718000?71ffff sa228 0 1 1 1 0 0 1 0 0 64/32 0e40000?0e4ffff 720000?727fff sa229 0 1 1 1 0 0 1 0 1 64/32 0e50000?0e5ffff 728000?72ffff sa230 0 1 1 1 0 0 1 1 0 64/32 0e60000?0e6ffff 730000?737fff sa231 0 1 1 1 0 0 1 1 1 64/32 0e70000?0e7ffff 738000?73ffff sa232 0 1 1 1 0 1 0 0 0 64/32 0e80000?0e8ffff 740000?747fff sa233 0 1 1 1 0 1 0 0 1 64/32 0e90000?0e9ffff 748000?74ffff sa234 0 1 1 1 0 1 0 1 0 64/32 0ea0000?0eaffff 750000?757fff sa235 0 1 1 1 0 1 0 1 1 64/32 0eb0000?0ebffff 758000?75ffff sa236 0 1 1 1 0 1 1 0 0 64/32 0ec0000?0ecffff 760000?767fff sa237 0 1 1 1 0 1 1 0 1 64/32 0ed0000?0edffff 768000?76ffff sa238 0 1 1 1 0 1 1 1 0 64/32 0ee0000?0eeffff 770000?777fff sa239 011101111 64/32 0ef0000?0efffff 778000?77ffff sa240 01111 0000 64/32 0f 00000?0f0ffff 780000?787fff sa241 011110001 64/32 0f10000?0f1ffff 788000?78ffff sa242 011110010 64/32 0f20000?0f2ffff 790 000?797fff sa243 011110011 64/32 0f30000?0f3 ffff 798000?79ffff sa244 011110100 64/32 0f40000?0f4ffff 7a0 000?7a7fff sa245 011110101 64/32 0f50000?0f5ffff 7a8000?7affff sa246 011110110 64/32 0f60000?0f6ffff 7b0 000?7b7fff sa247 011110111 64/32 0f70000?0f7ffff 7b8000?7bffff sa248 011111000 64/32 0f80000?0f8ffff 7c0 000?7c7fff sa249 011111001 64/32 0f90000?0f9ffff 7c8000?7cffff sa250 011111010 64/32 0fa0000?0faffff 7d0 000?7d7fff sa251 011111011 64/32 0fb0000?0fbffff 7d8000?7dffff sa252 011111100 64/32 0fc0000?0fc ffff 7e0000? 7e7fff sa253 011111101 64/32 0fd0000?0fdffff 7e8000?7effff sa254 011111110 64/32 0fe0000?0feffff 7f0 000?7f7fff sa255 011111111 64/32 0ff0000?0ffffff 7f8000?7f ffff sa256 1 00000000 64/32 10 00000?100ffff 800000?807fff sa257 1 0000000 1 64/32 1010000?101ffff 808000?80ffff sa258 1 000000 1 0 64/32 1020000?102ffff 810 000?817fff sa259 1 000000 1 1 64/32 1030000?103ffff 818000?81ffff sa260 1 00000 1 00 64/32 1040000?104ffff 820 000?827fff sa261 1 00000 1 0 1 64/32 1050000?105ffff 828000?82ffff sa262 1 00000 1 1 0 64/32 1060000?106ffff 830 000?837fff sa263 1 00000 1 1 1 64/32 1070000?107ffff 838000?83 ffff sa264 1 0000 1 000 64/32 1080000?108ffff 840 000?847fff sa265 1 0000 1 00 1 64/32 1090000?109ffff 848000?84ffff sa266 1 0000 1 0 1 0 64/32 10a0000?10affff 850 000?857fff sa267 1 0000 1 0 1 1 64/32 10b0000?10bffff 858000?85ffff sa268 1 0000 1 1 00 64/32 10c0000?10cffff 860 000?867fff sa269 1 0000 1 1 0 1 64/32 10d0000?10dffff 868000?86ffff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
72 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa270 1 0000 1 1 1 0 64/32 10e0000?10effff 870 000?877fff sa271 1 0000 1111 64/32 10f0000?10fffff 878000?87ffff sa272 1 000 1 0000 64/32 11 00000?110ffff 880000?887fff sa273 1 0 0 0 1 0 0 0 1 64/32 1110000?111ffff 888000?88ffff sa274 1 0 0 0 1 0 0 1 0 64/32 1120000?112ffff 890000?897fff sa275 1 0 0 0 1 0 0 1 1 64/32 1130000?113ffff 898000?89ffff sa276 1 0 0 0 1 0 1 0 0 64/32 1140000?114ffff 8a0000?8a7fff sa277 1 0 0 0 1 0 1 0 1 64/32 1150000?115ffff 8a8000?8affff sa278 1 0 0 0 1 0 1 1 0 64/32 1160000?116ffff 8b0000?8b7fff sa279 1 0 0 0 1 0 1 1 1 64/32 1170000?117ffff 8b8000?8bffff sa280 1 0 0 0 1 1 0 0 0 64/32 1180000?118ffff 8c0000?8c7fff sa281 1 0 0 0 1 1 0 0 1 64/32 1190000?119ffff 8c8000?8cffff sa282 1 0 0 0 1 1 0 1 0 64/32 11a0000?11affff 8d0000?8d7fff sa283 1 0 0 0 1 1 0 1 1 64/32 11b0000?11bffff 8d8000?8dffff sa284 1 0 0 0 1 1 1 0 0 64/32 11c0000?11cffff 8e0000?8e7fff sa285 1 0 0 0 1 1 1 0 1 64/32 11d0000?11dffff 8e8000?8effff sa286 100011110 64/32 11e0000?11effff 8f0 000?8f7fff sa287 100011111 64/32 11f0000?11fffff 8f8000?8fffff sa288 1 00 1 00000 64/32 12 00000?120ffff 900000?907fff sa289 1 00 1 0000 1 64/32 1210000?121ffff 908000?90ffff sa290 1 0 0 1 0 0 0 1 0 64/32 1220000?122ffff 910000?917fff sa291 1 0 0 1 0 0 0 1 1 64/32 1230000?123ffff 918000?91ffff sa292 1 0 0 1 0 0 1 0 0 64/32 1240000?124ffff 920000?927fff sa293 1 0 0 1 0 0 1 0 1 64/32 1250000?125ffff 928000?92ffff sa294 1 0 0 1 0 0 1 1 0 64/32 1260000?126ffff 930000?937fff sa295 1 0 0 1 0 0 1 1 1 64/32 1270000?127ffff 938000?93ffff sa296 1 0 0 1 0 1 0 0 0 64/32 1280000?128ffff 940000?947fff sa297 1 0 0 1 0 1 0 0 1 64/32 1290000?129ffff 948000?94ffff sa298 1 0 0 1 0 1 0 1 0 64/32 12a0000?12affff 950000?957fff sa299 1 0 0 1 0 1 0 1 1 64/32 12b0000?12bffff 958000?95ffff sa300 1 0 0 1 0 1 1 0 0 64/32 12c0000?12cffff 960000?967fff sa301 1 0 0 1 0 1 1 0 1 64/32 12d0000?12dffff 968000?96ffff sa302 1 0 0 1 0 1 1 1 0 64/32 12e0000?12effff 970000?977fff sa303 100101111 64/32 12f0000?12fffff 978000?97ffff sa304 1 00 1 1 0000 64/32 13 00000?130ffff 980000?987fff sa305 1 0 0 1 1 0 0 0 1 64/32 1310000?131ffff 988000?98ffff sa306 1 0 0 1 1 0 0 1 0 64/32 1320000?132ffff 990000?997fff sa307 1 0 0 1 1 0 0 1 1 64/32 1330000?133ffff 998000?99ffff sa308 1 0 0 1 1 0 1 0 0 64/32 1340000?134ffff 9a0000?9a7fff sa309 1 0 0 1 1 0 1 0 1 64/32 1350000?135ffff 9a8000?9affff sa310 1 0 0 1 1 0 1 1 0 64/32 1360000?136ffff 9b0000?9b7fff sa311 1 0 0 1 1 0 1 1 1 64/32 1370000?137ffff 9b8000?9bffff sa312 1 0 0 1 1 1 0 0 0 64/32 1380000?138ffff 9c0000?9c7fff sa313 1 0 0 1 1 1 0 0 1 64/32 1390000?139ffff 9c8000?9cffff sa314 1 0 0 1 1 1 0 1 0 64/32 13a0000?13affff 9d0000?9d7fff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 73 preliminary sa315 1 0 0 1 1 1 0 1 1 64/32 13b0000?13bffff 9d8000?9dffff sa316 100111100 64/32 13c0000?13c ffff 9e0000? 9e7fff sa317 100111101 64/32 13d0000?13dffff 9e8000?9effff sa318 100111110 64/32 13e0000?13effff 9f0 000?9f7fff sa319 100111111 64/32 13f0000?13fffff 9f8000?9fffff sa320 1 0 1 000000 64/32 14 00000?140ffff a00000?a07fff sa321 1 0 1 00000 1 64/32 1410000?141ffff a08000?a0ffff sa322 1 0 1 0000 1 0 64/32 1420000?142ffff a10 000?a17fff sa323 1 0 1 0000 1 1 64/32 1430000?143ffff a18000?a1ffff sa324 1 0 1 0 0 0 1 0 0 64/32 1440000?144ffff a20000?a27fff sa325 1 0 1 0 0 0 1 0 1 64/32 1450000?145ffff a28000?a2ffff sa326 1 0 1 0 0 0 1 1 0 64/32 1460000?146ffff a30000?a37fff sa327 1 0 1 0 0 0 1 1 1 64/32 1470000?147ffff a38000?a3ffff sa328 1 0 1 0 0 1 0 0 0 64/32 1480000?148ffff a40000?a47fff sa329 1 0 1 0 0 1 0 0 1 64/32 1490000?149ffff a48000?a4ffff sa330 1 0 1 0 0 1 0 1 0 64/32 14a0000?14affff a50000?a57fff sa331 1 0 1 0 0 1 0 1 1 64/32 14b0000?14bffff a58000?a5ffff sa332 1 0 1 0 0 1 1 0 0 64/32 14c0000?14cffff a60000?a67fff sa333 1 0 1 0 0 1 1 0 1 64/32 14d0000?14dffff a68000?a6ffff sa334 1 0 1 0 0 1 1 1 0 64/32 14e0000?14effff a70000?a77fff sa335 101001111 64/32 14f0000?14 fffff a78000?a7ffff sa336 1 0 1 0 1 0000 64/32 15 00000?150ffff a80000?a87fff sa337 1 0 1 0 1 0 0 0 1 64/32 1510000?151ffff a88000?a8ffff sa338 1 0 1 0 1 0 0 1 0 64/32 1520000?152ffff a90000?a97fff sa339 1 0 1 0 1 0 0 1 1 64/32 1530000?153ffff a98000?a9ffff sa340 1 0 1 0 1 0 1 0 0 64/32 1540000?154ffff aa0000?aa7fff sa341 101010101 64/32 1550000?155ffff aa8000?aaffff sa342 1 0 1 0 1 0 1 1 0 64/32 1560000?156ffff ab0000?ab7fff sa343 1 0 1 0 1 0 1 1 1 64/32 1570000?157ffff ab8000?abffff sa344 1 0 1 0 1 1 0 0 0 64/32 1580000?158ffff ac0000?ac7fff sa345 1 0 1 0 1 1 0 0 1 64/32 1590000?159ffff ac8000?acffff sa346 1 0 1 0 1 1 0 1 0 64/32 15a0000?15affff ad0000?ad7fff sa347 1 0 1 0 1 1 0 1 1 64/32 15b0000?15bffff ad8000?adffff sa348 1 0 1 0 1 1 1 0 0 64/32 15c0000?15cffff ae0000?ae7fff sa349 1 0 1 0 1 1 1 0 1 64/32 15d0000?15dffff ae8000?aeffff sa350 101011110 64/32 15e0000?15effff af0 000?af7fff sa351 101011111 64/32 15f0000?15f ffff af8000?afffff sa352 1 0 1 1 00000 64/32 16 00000?160ffff b00000?b07fff sa353 1 0 1 1 0000 1 64/32 1610000?161ffff b08000?b0ffff sa354 1 0 1 1 0 0 0 1 0 64/32 1620000?162ffff b10000?b17fff sa355 1 0 1 1 0 0 0 1 1 64/32 1630000?163ffff b18000?b1ffff sa356 1 0 1 1 0 0 1 0 0 64/32 1640000?164ffff b20000?b27fff sa357 1 0 1 1 0 0 1 0 1 64/32 1650000?165ffff b28000?b2ffff sa358 1 0 1 1 0 0 1 1 0 64/32 1660000?166ffff b30000?b37fff sa359 1 0 1 1 0 0 1 1 1 64/32 1670000?167ffff b38000?b3ffff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
74 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa360 1 0 1 1 0 1 0 0 0 64/32 1680000?168ffff b40000?b47fff sa361 1 0 1 1 0 1 0 0 1 64/32 1690000?169ffff b48000?b4ffff sa362 1 0 1 1 0 1 0 1 0 64/32 16a0000?16affff b50000?b57fff sa363 1 0 1 1 0 1 0 1 1 64/32 16b0000?16bffff b58000?b5ffff sa364 1 0 1 1 0 1 1 0 0 64/32 16c0000?16cffff b60000?b67fff sa365 1 0 1 1 0 1 1 0 1 64/32 16d0000?16dffff b68000?b6ffff sa366 1 0 1 1 0 1 1 1 0 64/32 16e0000?16effff b70000?b77fff sa367 101101111 64/32 16f0000?16fffff b78000?b7ffff sa368 1 0 1 1 1 0000 64/32 17 00000?170ffff b80000?b87fff sa369 1 0 1 1 1 0 0 0 1 64/32 1710000?171ffff b88000?b8ffff sa370 1 0 1 1 1 0 0 1 0 64/32 1720000?172ffff b90000?b97fff sa371 1 0 1 1 1 0 0 1 1 64/32 1730000?173ffff b98000?b9ffff sa372 1 0 1 1 1 0 1 0 0 64/32 1740000?174ffff ba0000?ba7fff sa373 1 0 1 1 1 0 1 0 1 64/32 1750000?175ffff ba8000?baffff sa374 1 0 1 1 1 0 1 1 0 64/32 176 0000?176ffff bb0000?bb 7fff sa375 1 0 1 1 1 0 1 1 1 64/32 1770000?177ffff bb8000?bbffff sa376 101111000 64/32 1780000?178ffff bc0 000?bc7fff sa377 101111001 64/32 1790000?179ffff bc8000?bcffff sa378 101111010 64/32 17a0000?17affff bd0 000?bd7fff sa379 101111011 64/32 17b0000?17bffff bd8000?bd ffff sa380 101111100 64/32 17c0000?17cffff be0 000?be7fff sa381 101111101 64/32 17d0000?17dffff be8000?beffff sa382 101111110 64/32 17e0000?17effff bf0 000?bf7fff sa383 101111111 64/32 17f0000?17f ffff bf8000?bfffff sa384 1 1 0000000 64/32 18 00000?180ffff c00000?c07fff sa385 1 1 000000 1 64/32 1810000?181ffff c08000?c0ffff sa386 1 1 00000 1 0 64/32 1820000?182ffff c10 000?c17fff sa387 1 1 00000 1 1 64/32 1830000?183ffff c18000?c1ffff sa388 1 1 0000 1 00 64/32 1840000?184ffff c20 000?c27fff sa389 1 1 0000 1 0 1 64/32 1850000?185ffff c28000?c2ffff sa390 1 1 0000 1 1 0 64/32 1860000?186ffff c30 000?c37fff sa391 1 1 0000 1 1 1 64/32 1870000?187ffff c38000?c3 ffff sa392 1 1 0 0 0 1 0 0 0 64/32 1880000?188ffff c40000?c47fff sa393 1 1 0 0 0 1 0 0 1 64/32 1890000?189ffff c48000?c4ffff sa394 1 1 0 0 0 1 0 1 0 64/32 18a0000?18affff c50000?c57fff sa395 1 1 0 0 0 1 0 1 1 64/32 18b0000?18bffff c58000?c5ffff sa396 1 1 0 0 0 1 1 0 0 64/32 18c0000?18cffff c60000?c67fff sa397 1 1 0 0 0 1 1 0 1 64/32 18d0000?18dffff c68000?c6ffff sa398 1 1 0 0 0 1 1 1 0 64/32 18e0000?18effff c70000?c77fff sa399 110001111 64/32 18f0000?18fffff c78000?c7ffff sa400 1 1 00 1 0000 64/32 19 00000?190ffff c80000?c87fff sa401 1 1 0 0 1 0 0 0 1 64/32 1910000?191ffff c88000?c8ffff sa402 1 1 0 0 1 0 0 1 0 64/32 1920000?192ffff c90000?c97fff sa403 1 1 0 0 1 0 0 1 1 64/32 1930000?193ffff c98000?c9ffff sa404 1 1 0 0 1 0 1 0 0 64/32 1940000?194ffff ca0000?ca7fff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 75 preliminary sa405 1 1 0 0 1 0 1 0 1 64/32 1950000?195ffff ca8000?caffff sa406 1 1 0 0 1 0 1 1 0 64/32 1960000?196ffff cb0000?cb7fff sa407 1 1 0 0 1 0 1 1 1 64/32 1970000?197ffff cb8000?cbffff sa408 1 1 0 0 1 1 0 0 0 64/32 1980000?198ffff cc0000?cc7fff sa409 1 1 0 0 1 1 0 0 1 64/32 1990000?199ffff cc8000?ccffff sa410 1 1 0 0 1 1 0 1 0 64/32 19a0000?19affff cd0000?cd7fff sa411 1 1 0 0 1 1 0 1 1 64/32 19b0000?19bffff cd8000?cdffff sa412 1 1 0 0 1 1 1 0 0 64/32 19c0000?19cffff ce0000?ce7fff sa413 1 1 0 0 1 1 1 0 1 64/32 19d0000?19dffff ce8000?ceffff sa414 110011110 64/32 19e0000?19effff cf0 000?cf7fff sa415 110011111 64/32 19f0000?19fffff cf8000?cfffff sa416 1 1 0 1 00000 64/32 1a 00000?1a0ffff d00000?d07fff sa417 1 1 0 1 0000 1 64/32 1a10000?1a1ffff d08000?d0ffff sa418 1 1 0 1 0 0 0 1 0 64/32 1a20000?1a2ffff d10000?d17fff sa419 1 1 0 1 0 0 0 1 1 64/32 1a30000?1a3ffff d18000?d1ffff sa420 1 1 0 1 0 0 1 0 0 64/32 1a40000?1a4ffff d20000?d27fff sa421 1 1 0 1 0 0 1 0 1 64/32 1a50000?1a5ffff d28000?d2ffff sa422 1 1 0 1 0 0 1 1 0 64/32 1a60000?1a6ffff d30000?d37fff sa423 1 1 0 1 0 0 1 1 1 64/32 1a70000?1a7ffff d38000?d3ffff sa424 1 1 0 1 0 1 0 0 0 64/32 1a80000?1a8ffff d40000?d47fff sa425 1 1 0 1 0 1 0 0 1 64/32 1a90000?1a9ffff d48000?d4ffff sa426 1 1 0 1 0 1 0 1 0 64/32 1aa0000?1aaffff d50000?d57fff sa427 1 1 0 1 0 1 0 1 1 64/32 1ab0000?1abffff d58000?d5ffff sa428 1 1 0 1 0 1 1 0 0 64/32 1ac0000?1acffff d60000?d67fff sa429 1 1 0 1 0 1 1 0 1 64/32 1ad0000?1adffff d68000?d6ffff sa430 1 1 0 1 0 1 1 1 0 64/32 1ae0000?1aeffff d70000?d77fff sa431 110101111 64/32 1af0000?1afffff d78000?d7ffff sa432 1 1 0 1 1 0000 64/32 1b 00000?1b0ffff d80000?d87fff sa433 1 1 0 1 1 0 0 0 1 64/32 1b10000?1b1ffff d88000?d8ffff sa434 1 1 0 1 1 0 0 1 0 64/32 1b20000?1b2ffff d90000?d97fff sa435 1 1 0 1 1 0 0 1 1 64/32 1b30000?1b3ffff d98000?d9ffff sa436 1 1 0 1 1 0 1 0 0 64/32 1b40000?1b4ffff da0000?da7fff sa437 1 1 0 1 1 0 1 0 1 64/32 1b50000?1b5ffff da8000?daffff sa438 1 1 0 1 1 0 1 1 0 64/32 1b60000?1b6ffff db0000?db7fff sa439 1 1 0 1 1 0 1 1 1 64/32 1b70000?1b7ffff db8000?dbffff sa440 1 1 0 1 1 1 0 0 0 64/32 1b80000?1b8ffff dc0000?dc7fff sa441 1 1 0 1 1 1 0 0 1 64/32 1b90000?1b9ffff dc8000?dcffff sa442 1 1 0 1 1 1 0 1 0 64/32 1ba0000?1baffff dd0000?dd7fff sa443 1 1 0 1 1 1 0 1 1 64/32 1bb0000?1bbffff dd8000?ddffff sa444 110111100 64/32 1bc0000?1bcffff de0 000?de7fff sa445 110111101 64/32 1bd0000?1bd ffff de8000?deffff sa446 110111110 64/32 1be0000?1beffff df0 000?df7fff sa447 110111111 64/32 1bf0000?1bfffff df8000?dfffff sa448 1 1 1 000000 64/32 1c 00000?1c0ffff e00000?e07fff sa449 1 1 1 00000 1 64/32 1c10000?1c1ffff e08000?e0ffff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
76 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa450 1 1 1 0000 1 0 64/32 1c20000?1c2ffff e10 000?e17fff sa451 1 1 1 0000 1 1 64/32 1c30000?1c3 ffff e18000?e1ffff sa452 1 1 1 0 0 0 1 0 0 64/32 1c40000?1c4ffff e20000?e27fff sa453 1 1 1 0 0 0 1 0 1 64/32 1c50000?1c5ffff e28000?e2ffff sa454 1 1 1 0 0 0 1 1 0 64/32 1c60000?1c6ffff e30000?e37fff sa455 1 1 1 0 0 0 1 1 1 64/32 1c70000?1c7ffff e38000?e3ffff sa456 1 1 1 0 0 1 0 0 0 64/32 1c80000?1c8ffff e40000?e47fff sa457 1 1 1 0 0 1 0 0 1 64/32 1c90000?1c9ffff e48000?e4ffff sa458 1 1 1 0 0 1 0 1 0 64/32 1ca0000?1caffff e50000?e57fff sa459 1 1 1 0 0 1 0 1 1 64/32 1cb0000?1cbffff e58000?e5ffff sa460 1 1 1 0 0 1 1 0 0 64/32 1cc0000?1ccffff e60000?e67fff sa461 1 1 1 0 0 1 1 0 1 64/32 1cd0000?1cdffff e68000?e6ffff sa462 1 1 1 0 0 1 1 1 0 64/32 1ce0000?1ceffff e70000?e77fff sa463 111001111 64/32 1cf0000?1cfffff e78000?e7ffff sa464 1 1 1 0 1 0000 64/32 1d 00000?1d0ffff e80000?e87fff sa465 1 1 1 0 1 0 0 0 1 64/32 1d10000?1d1ffff e88000?e8ffff sa466 1 1 1 0 1 0 0 1 0 64/32 1d20000?1d2ffff e90000?e97fff sa467 1 1 1 0 1 0 0 1 1 64/32 1d30000?1d3ffff e98000?e9ffff sa468 1 1 1 0 1 0 1 0 0 64/32 1d40000?1d4ffff ea0000?ea7fff sa469 1 1 1 0 1 0 1 0 1 64/32 1d50000?1d5ffff ea8000?eaffff sa470 1 1 1 0 1 0 1 1 0 64/32 1d60000?1d6ffff eb0000?eb7fff sa471 1 1 1 0 1 0 1 1 1 64/32 1d70000?1d7ffff eb8000?ebffff sa472 1 1 1 0 1 1 0 0 0 64/32 1d80000?1d8ffff ec0000?ec7fff sa473 1 1 1 0 1 1 0 0 1 64/32 1d90000?1d9ffff ec8000?ecffff sa474 1 1 1 0 1 1 0 1 0 64/32 1da0000?1daffff ed0000?ed7fff sa475 1 1 1 0 1 1 0 1 1 64/32 1db0000?1dbffff ed8000?edffff sa476 1 1 1 0 1 1 1 0 0 64/32 1dc0000?1dcffff ee0000?ee7fff sa477 1 1 1 0 1 1 1 0 1 64/32 1dd0000?1ddffff ee8000?eeffff sa478 111011110 64/32 1de0000?1deffff ef0 000?ef7fff sa479 111011111 64/32 1df0000?1dfffff ef8000?efffff sa480 1111 00000 64/32 1e 00000?1e0ffff f00000?f07fff sa481 1111 0000 1 64/32 1e10000?1e1ffff f08000?f0ffff sa482 111100010 64/32 1e20000?1e2ffff f10 000?f17fff sa483 111100011 64/32 1e30000?1e3ffff f18000?f1ffff sa484 111100100 64/32 1e40000?1e4ffff f20 000?f27fff sa485 111100101 64/32 1e50000?1e5ffff f28000?f2ffff sa486 111100110 64/32 1e60000?1e6ffff f30 000?f37fff sa487 111100111 64/32 1e70000?1e7ffff f38000?f3ffff sa488 111101000 64/32 1e80000?1e8ffff f40 000?f47fff sa489 111101001 64/32 1e90000?1e9ffff f48000?f4ffff sa490 111101010 64/32 1ea0000?1eaffff f50 000?f57fff sa491 111101011 64/32 1eb0000?1ebffff f58000?f5 ffff sa492 111101100 64/32 1ec0000?1ecffff f60 000?f67fff sa493 111101101 64/32 1ed0000?1edffff f68000?f6ffff sa494 111101110 64/32 1ee0000?1eeffff f70 000?f77fff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 77 preliminary autoselect mode the autoselect mode provides manufacturer and device identification, and sector group protection verification, through identifier codes output on dq7?dq0. this mode is primarily intended for programming equipment to automatically match a device to be programmed with its co rresponding programming algorithm. how- ever, the autoselect codes can also be accessed in-system through the command register. when using programming equipment, the autoselect mode requires vid on ad- dress pin a9. address pins a6, a3, a2, a1, and a0 must be as shown in tables 14- . in addition, when verifying sector protection, the sector address must ap- pear on the appropriate highest order address bits (see table 2 ). tables 14- shows the remaining address bits that are don?t care. when all necessary bits have been set as required, the programming equipment may then read the cor- responding identifier code on dq7?dq0. to access the autoselect codes in-system, the host system can issue the autose- lect command via the command register, as shown in table 31 and table 32 . this method does not require v id . refer to the autoselect command sequence section for more information. sa495 111101111 64/32 1ef0000?1efffff f78000?f7 ffff sa496 11111 0000 64/32 1f 00000?1f0ffff f80000?f87fff sa497 111110001 64/32 1f10000?1f1ffff f88000?f8ffff sa498 111110010 64/32 1f20000?1f2ffff f90 000?f97fff sa499 111110011 64/32 1f30000?1f3ffff f98000?f9ffff sa500 111110100 64/32 1f40000?1f4ffff fa0 000?fa7fff sa501 111110101 64/32 1f50000?1f5 ffff fa8000?faffff sa502 111110110 64/32 1f60000?1f6ffff fb0 000?fb7fff sa503 111110111 64/32 1f70000?1f7 ffff fb8000?fbffff sa504 111111000 64/32 1f80000?1f8ffff fc0 000?fc7fff sa505 111111001 64/32 1f90000?1f9ffff fc8000?fcffff sa506 111111010 64/32 1fa0000?1faffff fd0 000?fd7fff sa507 111111011 64/32 1fb0000?1fbffff fd8000?fdffff sa508 111111100 64/32 1fc0000?1fcffff fe0 000?fe7fff sa509 111111101 64/32 1fd0000?1fdffff fe8000?feffff sa510 111111110 64/32 1fe0000?1feffff ff0 000?ff7fff sa511 111111111 64/32 1ff0000?1ffffff ff8000?ffffff table 13. s29gl256m sector address table (continued) sector a23?a15 sector size (kbytes/kwords) 8-bit address range (in hexadecimal) 16-bit address range (in hexadecimal)
78 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ta b l e 1 4 . autoselect codes, (high voltage method) legend: l = logic low = v il , h = logic high = v ih , sa = sector address, x = don?t care. sector group protection and unprotection the hardware sector group protection feature disables both program and erase operations in any sector group. in this device, a sector group consists of four ad- jacent sectors that are protected or unprotected at the same time (see ta b l e 4 ). the hardware sector group unprotection feature re-enables both program and erase operations in previously protected sector groups. sector group protection/ unprotection can be implemented via two methods. sector protection/unprotection requires v id on the reset# pin only, and can be implemented either in-system or via programming equipment. figure 2 shows the algorithms and figure 24 shows the timing diagram. this method uses stan- dard microprocessor bus cycle timing. for sector group unprotect, all unprotected sector groups must first be protected pr ior to the first sector group unprotect write cycle. the device is shipped with all sector groups unprotected. fasl offers the option of programming and protecting sector grou ps at its factory prior to shipping the device through spansion? programming services. contact your sales represen- tative for details. it is possible to determine whether a sector group is protected or unprotected. see the autoselect mode section for details. description ce# oe# we# a22 to a15 a14 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 dq8 to dq15 dq7 to dq0 model number byte# = v ih byte# = v il r0 r1, r2 r3, r4 r5, r6, r7 manufacturer id : fasl llhxx v id x l x l l l 00 x 01h 01h 01h 01h s29gl256 cycle 1 llhxx v id xlx llh 22 x 7eh cycle 2 hh l 22 x 12h cycle 3 hhh 22 x 01h s29gl128n cycle 1 llhxx v id xlx llh 22 x 7eh 7eh cycle 2 hh l 22 x 12h 22h cycle 3 hhh 22 x 00h 01h s29gl064n cycle 1 llhxx v id xlx l l h 22 x 7eh 7eh 7eh 7eh cycle 2 hh l 22 x 13h 0ch 10h 13h cycle 3 h h h 22 x 00h 01h 00h (r4 bottom boot) 01h (r3 top boot) 01h s29gl032n cycle 1 llhxx v id xlx l l h 22 x 7eh 7eh 7eh cycle 2 hh l 22 x 1ch 1dh 23h cycle 3 hhh 22 x 00h 00h 00h (r4 bottom boot) 01h (r3 top boot) sector group protection verification llhsax v id xlxlhl x x 01h (protected), 00h (unprotected) secsi sector indicator bit (dq7), wp# protects highest address sector llhxx v id xlxlhh x x 98h (factory locked), 18h (not factory locked) secsi sector indicator bit (dq7), wp# protects lowest address sector llhxx v id xlxlhh x x 88h (factory locked), 08h (not factory locked)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 79 preliminary ta b l e 1 5 . s29gl032m (model r0) sector group protection/unprotection address ta b l e note: all sector groups are 256 kbytes in size. sector group a22?a18 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 table 16. s29gl032m (model r1) top boot sector protection sector a20?a12 sector/ sector block size sa0-sa3 0000xxxxxh 256 (4x64) kbytes sa4-sa7 0001xxxxxh 256 (4x64) kbytes sa8-sa11 0010xxxxxh 256 (4x64) kbytes sa12-sa15 0011xxxxxh 256 (4x64) kbytes sa16-sa19 0100xxxxxh 256 (4x64) kbytes sa20-sa23 0101xxxxxh 256 (4x64) kbytes sa24-sa27 0110xxxxxh 256 (4x64) kbytes sa28-sa31 0111xxxxxh 256 (4x64) kbytes sa32?sa35 1000xxxxxh, 256 (4x64) kbytes sa36?sa39 1001xxxxxh 256 (4x64) kbytes sa40?sa43 1010xxxxxh 256 (4x64) kbytes sa44?sa47 1011xxxxxh 256 (4x64) kbytes sa48?sa51 1100xxxxxh 256 (4x64) kbytes sa52-sa55 1101xxxxxh 256 (4x64) kbytes sa56-sa59 1110xxxxxh 256 (4x64) kbytes sa60-sa62 111100xxxh 111101xxxh 111110xxxh 192 (3x64) kbytes sa63 111111000h 8 kbytes sa64 111111001h 8 kbytes sa65 111111010h 8 kbytes sa66 111111011h 8 kbytes
80 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa67 111111100h 8 kbytes sa68 111111101h 8 kbytes sa69 111111110h 8 kbytes sa70 111111111h 8 kbytes ta b l e 1 7 . s29gl032m (model r2) bottom boot sector protection sector a20?a12 sector/ sector block size sa0 000000000h 8 kbytes sa1 000000001h 8 kbytes sa2 000000010h 8 kbytes sa3 000000011h 8 kbytes sa4 000000100h 8 kbytes sa5 000000101h 8 kbytes sa6 000000110h 8 kbytes sa7 000000111h 8 kbytes sa8?sa10 000001xxxh, 000010xxxh, 000011xxxh, 192 (3x64) kbytes sa11?sa14 0001xxxxxh 256 (4x64) kbytes sa15?sa18 0010xxxxxh 256 (4x64) kbytes sa19?sa22 0011xxxxxh 256 (4x64) kbytes sa23?sa26 0100xxxxxh 256 (4x64) kbytes sa27-sa30 0101xxxxxh 256 (4x64) kbytes sa31-sa34 0110xxxxxh 256 (4x64) kbytes sa35-sa38 0111xxxxxh 256 (4x64) kbytes sa39-sa42 1000xxxxxh 256 (4x64) kbytes sa43-sa46 1001xxxxxh 256 (4x64) kbytes sa47-sa50 1010xxxxxh 256 (4x64) kbytes sa51-sa54 1011xxxxxh 256 (4x64) kbytes sa55?sa58 1100xxxxxh 256 (4x64) kbytes sa59?sa62 1101xxxxxh 256 (4x64) kbytes sa63?sa66 1110xxxxxh 256 (4x64) kbytes sa67?sa70 1111xxxxxh 256 (4x64) kbytes table 16. s29gl032m (model r1) top boot sector protection (continued) sector a20?a12 sector/ sector block size
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 81 preliminary ta b l e 1 8 . s29gl032m (models r3, r4) sector group protection/unprotection address ta b l e sector group a20?a15 sa0 000000 sa1 000001 sa2 000010 sa3 000011 sa4?sa7 0001xx sa8?sa11 0010xx sa12?sa15 0011xx sa16?sa19 0100xx sa20?sa23 0101xx sa24?sa27 0110xx sa28?sa31 0111xx sa32?sa35 1000xx sa36?sa39 1001xx sa40?sa43 1010xx sa44?sa47 1011xx sa48?sa51 1100xx sa52?sa55 1101xx sa56?sa59 1110xx sa60 111100 sa61 111101 sa62 111110 sa63 111111
82 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ta b l e 1 9 . s29gl065m (model r0) sector group protection/unprotection address ta b l e note: all sector groups are 256 kbytes in size. sector group a22?a18 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 83 preliminary ta b l e 2 0 . s29gl064m (model r1) top boot sector protection sector a21?a12 sector/ sector block size sa0-sa3 00000xxxxx 256 (4x64) kbytes sa4-sa7 00001xxxxx 256 (4x64) kbytes sa8-sa11 00010xxxxx 256 (4x64) kbytes sa12-sa15 00011xxxxx 256 (4x64) kbytes sa16-sa19 00100xxxxx 256 (4x64) kbytes sa20-sa23 00101xxxxx 256 (4x64) kbytes sa24-sa27 00110xxxxx 256 (4x64) kbytes sa28-sa31 00111xxxxx 256 (4x64) kbytes sa32-sa35 01000xxxxx 256 (4x64) kbytes sa36-sa39 01001xxxxx 256 (4x64) kbytes sa40-sa43 01010xxxxx 256 (4x64) kbytes sa44-sa47 01011xxxxx 256 (4x64) kbytes sa48-sa51 01100xxxxx 256 (4x64) kbytes sa52-sa55 01101xxxxx 256 (4x64) kbytes sa56-sa59 01110xxxxx 256 (4x64) kbytes sa60-sa63 01111xxxxx 256 (4x64) kbytes sa64-sa67 10000xxxxx 256 (4x64) kbytes sa68-sa71 10001xxxxx 256 (4x64) kbytes sa72-sa75 10010xxxxx 256 (4x64) kbytes sa76-sa79 10011xxxxx 256 (4x64) kbytes sa80-sa83 10100xxxxx 256 (4x64) kbytes sa84-sa87 10101xxxxx 256 (4x64) kbytes sa88-sa91 10110xxxxx 256 (4x64) kbytes sa92-sa95 10111xxxxx 256 (4x64) kbytes sa96-sa99 11000xxxxx 256 (4x64) kbytes sa100-sa103 11001xxxxx 256 (4x64) kbytes sa104-sa107 11010xxxxx 256 (4x64) kbytes sa108-sa111 11011xxxxx 256 (4x64) kbytes sa112-sa115 11100xxxxx 256 (4x64) kbytes sa116-sa119 11101xxxxx 256 (4x64) kbytes sa120-sa123 11110xxxxx 256 (4x64) kbytes sa124-sa126 1111100xxx 1111101xxx 1111110xxx 192 (3x64) kbytes sa127 1111111000 8 kbytes sa128 1111111001 8 kbytes sa129 1111111010 8 kbytes sa130 1111111011 8 kbytes sa131 1111111100 8 kbytes sa132 1111111101 8 kbytes sa133 1111111110 8 kbytes sa134 1111111111 8 kbytes
84 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ta b l e 2 1 . s29gl064m (model r2) bottom boot sector protection sector a21?a12 sector/ sector block size sa0 0000000000 8 kbytes sa1 0000000001 8 kbytes sa2 0000000010 8 kbytes sa3 0000000011 8 kbytes sa4 0000000100 8 kbytes sa5 0000000101 8 kbytes sa6 0000000110 8 kbytes sa7 0000000111 8 kbytes sa8?sa10 0000001xxx, 0000010xxx, 0000011xxx, 192 (3x64) kbytes sa11?sa14 00001xxxxx 256 (4x64) kbytes sa15?sa18 00010xxxxx 256 (4x64) kbytes sa19?sa22 00011xxxxx 256 (4x64) kbytes sa23?sa26 00100xxxxx 256 (4x64) kbytes sa27-sa30 00101xxxxx 256 (4x64) kbytes sa31-sa34 00110xxxxx 256 (4x64) kbytes sa35-sa38 00111xxxxx 256 (4x64) kbytes sa39-sa42 01000xxxxx 256 (4x64) kbytes sa43-sa46 01001xxxxx 256 (4x64) kbytes sa47-sa50 01010xxxxx 256 (4x64) kbytes sa51-sa54 01011xxxxx 256 (4x64) kbytes sa55?sa58 01100xxxxx 256 (4x64) kbytes sa59?sa62 01101xxxxx 256 (4x64) kbytes sa63?sa66 01110xxxxx 256 (4x64) kbytes sa67?sa70 01111xxxxx 256 (4x64) kbytes sa71?sa74 10000xxxxx 256 (4x64) kbytes sa75?sa78 10001xxxxx 256 (4x64) kbytes sa79?sa82 10010xxxxx 256 (4x64) kbytes sa83?sa86 10011xxxxx 256 (4x64) kbytes sa87?sa90 10100xxxxx 256 (4x64) kbytes sa91?sa94 10101xxxxx 256 (4x64) kbytes sa95?sa98 10110xxxxx 256 (4x64) kbytes sa99?sa102 10111xxxxx 256 (4x64) kbytes sa103?sa106 11000xxxxx 256 (4x64) kbytes sa107?sa110 11001xxxxx 256 (4x64) kbytes sa111?sa114 11010xxxxx 256 (4x64) kbytes sa115?sa118 11011xxxxx 256 (4x64) kbytes sa119?sa122 11100xxxxx 256 (4x64) kbytes sa123?sa126 11101xxxxx 256 (4x64) kbytes sa127?sa130 11110xxxxx 256 (4x64) kbytes sa131?sa134 11111xxxxx 256 (4x64) kbytes
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 85 preliminary ta b l e 2 2 . s29gl064m (model r3, r4) sector group protection/unprotection address ta b l e sector group a21?a15 sa0 0000000 sa1 0000001 sa2 0000010 sa3 0000011 sa4?sa7 00001xx sa8?sa11 00010xx sa12?sa15 00011xx sa16?sa19 00100xx sa20?sa23 00101xx sa24?sa27 00110xx sa28?sa31 00111xx sa32?sa35 01000xx sa36?sa39 01001xx sa40?sa43 01010xx sa44?sa47 01011xx sa48?sa51 01100xx sa52?sa55 01101xx sa56?sa59 01110xx sa60?sa63 01111xx sa64?sa67 10000xx sa68?sa71 10001xx sa72?sa75 10010xx sa76?sa79 10011xx sa80?sa83 10100xx sa84?sa87 10101xx sa88?sa91 10110xx sa92?sa95 10111xx sa96?sa99 11000xx sa100?sa103 11001xx sa104?sa107 11010xx sa108?sa111 11011xx sa112?sa115 11100xx sa116?sa119 11101xx sa120?sa123 11110xx sa124 1111100 sa125 1111101 sa126 1111110 sa127 1111111
86 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ta b l e 2 3 . s29gl064m (model r5) sector group protection/unprotection address ta b l e note: all sector groups are 128 kwords in size. sector group a21?a17 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 87 preliminary ta b l e 2 4 . s29gl064m (models r6, r7) sector group protection/unprotection address ta b l e note: all sector groups are 128 kwords in size. sector group a21?a17 sa0?sa3 00000 sa4?sa7 00001 sa8?sa11 00010 sa12?sa15 00011 sa16?sa19 00100 sa20?sa23 00101 sa24?sa27 00110 sa28?sa31 00111 sa32?sa35 01000 sa36?sa39 01001 sa40?sa43 01010 sa44?sa47 01011 sa48?sa51 01100 sa52?sa55 01101 sa56?sa59 01110 sa60?sa63 01111 sa64?sa67 10000 sa68?sa71 10001 sa72?sa75 10010 sa76?sa79 10011 sa80?sa83 10100 sa84?sa87 10101 sa88?sa91 10110 sa92?sa95 10111 sa96?sa99 11000 sa100?sa103 11001 sa104?sa107 11010 sa108?sa111 11011 sa112?sa115 11100 sa116?sa119 11101 sa120?sa123 11110 sa124?sa127 11111 table 25. s29gl128m sector group protection/unprotection address table sector group a22?a15 sa0 00000000 sa1 00000001 sa2 00000010 sa3 00000011 sa4?sa7 000001xx
88 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa8?sa11 000010xx sa12?sa15 000011xx sa16?sa19 000100xx sa20?sa23 000101xx sa24?sa27 000110xx sa28?sa31 000111xx sa32?sa35 001000xx sa36?sa39 001001xx sa40?sa43 001010xx sa44?sa47 001011xx sa48?sa51 001100xx sa52?sa55 001101xx sa56?sa59 001110xx sa60?sa63 001111xx sa64?sa67 010000xx sa68?sa71 010001xx sa72?sa75 010010xx sa76?sa79 010011xx sa80?sa83 010100xx sa84?sa87 010101xx sa88?sa91 010110xx sa92?sa95 010111xx sa96?sa99 011000xx sa100?sa103 011001xx sa104?sa107 011010xx sa108?sa111 011011xx sa112?sa115 011100xx sa116?sa119 011101xx sa120?sa123 011110xx sa124?sa127 011111xx sa128?sa131 100000xx sa132?sa135 100001xx sa136?sa139 100010xx sa140?sa143 100011xx sa144?sa147 100100xx sa148?sa151 100101xx sa152?sa155 100110xx sa156?sa159 100111xx sa160?sa163 101000xx sa164?sa167 101001xx sa168?sa171 101010xx table 25. s29gl128m sector group protection/unprotection address table (continued) sector group a22?a15
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 89 preliminary sa172?sa175 101011xx sa176?sa179 101100xx sa180?sa183 101101xx sa184?sa187 101110xx sa188?sa191 101111xx sa192?sa195 110000xx sa196?sa199 110001xx sa200?sa203 110010xx sa204?sa207 110011xx sa208?sa211 110100xx sa212?sa215 110101xx sa216?sa219 110110xx sa220?sa223 110111xx sa224?sa227 111000xx sa228?sa231 111001xx sa232?sa235 111010xx sa236?sa239 111011xx sa240?sa243 111100xx sa244?sa247 111101xx sa248?sa251 111110xx sa252 11111100 sa253 11111101 sa254 11111110 sa255 11111111 table 26. s29gl256m sector group protection/unprotection address table sector group a23?a15 sa0 000000000 sa1 000000001 sa2 000000010 sa3 000000011 sa4?sa7 0000001xx sa8?sa11 0000010xx sa12?sa15 0000011xx sa16?sa19 0000100xx sa20?sa23 0000101xx sa24?sa27 0000110xx sa28?sa31 0000111xx sa32?sa35 0001000xx sa36?sa39 0001001xx table 25. s29gl128m sector group protection/unprotection address table (continued) sector group a22?a15
90 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa40?sa43 0001010xx sa44?sa47 0001011xx sa48?sa51 0001100xx sa52?sa55 0001101xx sa56?sa59 0001110xx sa60?sa63 0001111xx sa64?sa67 0010000xx sa68?sa71 0010001xx sa72?sa75 0010010xx sa76?sa79 0010011xx sa80?sa83 0010100xx sa84?sa87 0010101xx sa88?sa91 0010110xx sa92?sa95 0010111xx sa96?sa99 0011000xx sa100?sa103 0011001xx sa104?sa107 0011010xx sa108?sa111 0011011xx sa112?sa115 0011100xx sa116?sa119 0011101xx sa120?sa123 0011110xx sa124?sa127 0011111xx sa128?sa131 0100000xx sa132?sa135 0100001xx sa136?sa139 0100010xx sa140?sa143 0100011xx sa144?sa147 0100100xx sa148?sa151 0100101xx sa152?sa155 0100110xx sa156?sa159 0100111xx sa160?sa163 0101000xx sa164?sa167 0101001xx sa168?sa171 0101010xx sa172?sa175 0101011xx sa176?sa179 0101100xx sa180?sa183 0101101xx sa184?sa187 0101110xx sa188?sa191 0101111xx sa192?sa195 0110000xx sa196?sa199 0110001xx sa200?sa203 0110010xx table 26. s29gl256m sector group protection/unprotection address table (continued) sector group a23?a15
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 91 preliminary sa204?sa207 0110011xx sa208?sa211 0110100xx sa212?sa215 0110101xx sa216?sa219 0110110xx sa220?sa223 0110111xx sa224?sa227 0111000xx sa228?sa231 0111001xx sa232?sa235 0111010xx sa236?sa239 0111011xx sa240?sa243 0111100xx sa244?sa247 0111101xx sa248?sa251 0111110xx sa252?sa255 0111111xx sa256?sa259 1000000xx sa260?sa263 1000001xx sa264?sa267 1000010xx sa268?sa271 1000011xx sa272?sa275 1000100xx sa276?sa279 1000101xx sa280?sa283 1000110xx sa284?sa287 1000111xx sa288?sa291 1001000xx sa292?sa295 1001001xx sa296?sa299 1001010xx sa300?sa303 1001011xx sa304?sa307 1001100xx sa308?sa311 1001101xx sa312?sa315 1001110xx sa316?sa319 1001111xx sa320?sa323 1010000xx sa324?sa327 1010001xx sa328?sa331 1010010xx sa332?sa335 1010011xx sa336?sa339 1010100xx sa340?sa343 1010101xx sa344?sa347 1010110xx sa348?sa351 1010111xx sa352?sa355 1011000xx sa356?sa359 1011001xx sa360?sa363 1011010xx sa364?sa367 1011011xx table 26. s29gl256m sector group protection/unprotection address table (continued) sector group a23?a15
92 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sa368?sa371 1011100xx sa372?sa375 1011101xx sa376?sa379 1011110xx sa380?sa383 1011111xx sa384?sa387 1100000xx sa388?sa391 1100001xx sa392?sa395 1100010xx sa396?sa399 1100011xx sa400?sa403 1100100xx sa404?sa407 1100101xx sa408?sa411 1100110xx sa412?sa415 1100111xx sa416?sa419 1101000xx sa420?sa423 1101001xx sa424?sa427 1101010xx sa428?sa431 1101011xx sa432?sa435 1101100xx sa436?sa439 1101101xx sa440?sa443 1101110xx sa444?sa447 1101111xx sa448?sa451 1110000xx sa452?sa455 1110001xx sa456?sa459 1110010xx sa460?sa463 1110011xx sa464?sa467 1110100xx sa468?sa471 1110101xx sa472?sa475 1110110xx sa476?sa479 1110111xx sa480?sa483 1111000xx sa484?sa487 1111001xx sa488?sa491 1111010xx sa492?sa495 1111011xx sa496?sa499 1111100xx sa500?sa503 1111101xx sa504?sa507 1111110xx sa508 111111100 sa509 111111101 sa510 111111110 sa511 111111111 table 26. s29gl256m sector group protection/unprotection address table (continued) sector group a23?a15
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 93 preliminary temporary sector group unprotect this feature allows temporary unprotection of previously protected sector groups to change data in-system. the sector group unprotect mode is activated by set- ting the reset# pin to v id . during this mode, formerly protected sector groups can be programmed or erased by selecting the sector group addresses. once v id is removed from the reset# pin, all the previously protected sector groups are protected again. figure 1 shows the algo rithm, and figure 23 shows the timing diagrams, for this feature. notes: 1. all protected sector groups unprotected (if wp# = v il , the first or last sector will remain protected). 2. all previously protected sector groups are protected once again. figure 1. temporary sector group unprotect operation start perform erase or program operations reset# = v ih te m p o ra r y s e c t o r group unprotect completed (note 2) reset# = v id (note 1)
94 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary figure 2. in-system sector group protect/unprotect algorithms sector group protect: write 60h to sector group address with a6?a0 = 0xx0010 set up sector group address wait 150 s verify sector group protect: write 40h to sector group address with a6?a0 = 0xx0010 read from sector group address with a6?a0 = 0xx0010 start plscnt = 1 reset# = v id wait 1 s first write cycle = 60h? data = 01h? remove v id from reset# write reset command sector group protect complete yes yes no plscnt = 25? yes device failed increment plscnt temporary sector group unprotect mode no sector group unprotect: write 60h to sector group address with a6?a0 = 1xx0010 set up first sector group address wait 15 ms verify sector group unprotect: write 40h to sector group address with a6?a0 = 1xx0010 read from sector group address with a6?a0 = 1xx0010 start plscnt = 1 reset# = v id wait 1 s data = 00h? last sector group verified? remove v id from reset# write reset command sector group unprotect complete yes no plscnt = 1000? yes device failed increment plscnt temporary sector group unprotect mode no all sector groups protected? yes protect all sector groups: the indicated portion of the sector group protect algorithm must be performed for all unprotected sector groups prior to issuing the first sector group unprotect address set up next sector group address no yes no yes no no yes no sector group protect algorithm sector group unprotect algorithm first write cycle = 60h? protect another sector group? reset plscnt = 1
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 95 preliminary secsi (secured silicon) sector flash memory region the secsi (secured silicon) sector feature provides a flash memory region that enables permanent part identification through an electronic serial number (esn). the secsi sector is 256 bytes in length, and uses a secsi sector indicator bit (dq7) to indicate whether or not the secsi sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. this ensures the security of the esn once the product is shipped to the field. the factory offers the device with the secsi sector either customer lockable (standard shipping option) or factory locked (contact your sales representative for ordering information). the customer-lockable version is shipped with the secsi sector unprotected, allowing customers to program the sector after receiv- ing the device. the customer-lockable version also has the secsi sector indicator bit permanently set to a ?0.? the factory-locked version is always protected when shipped from the factory, and has the secsi (secured silicon) sector indicator bit permanently set to a ?1.? thus, the secsi sector indicator bit prevents customer- lockable devices from being used to replace devices that are factory locked. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. the secsi sector address space in this device is allocated as follows: the system accesses the secsi sector through a command sequence (see ?write protect (wp#)?). after the system has written the enter secsi sector command sequence, it may read the secsi sector by using the addresses normally occupied by the first sector (sa0). this mode of operation continues until the system issues the exit secsi sector command sequence, or until power is removed from the de- vice. on power-up, or following a hardware reset, the device reverts to sending commands to sector sa0. customer lockable: secsi sector not programmed or protected at the factory unless otherwise specified, the device is shipped such that the customer may program and protect the 256-byte secsi sector. the system may program the secsi sector using the write-buffer, accelerated and/or unlock bypass methods, in addition to the standard programming com- mand sequence. see command definitions. programming and protecting the secsi sector must be used with caution since, once protected, there is no procedure available for unprotecting the secsi sector area and none of the bits in the secsi sector memory space can be modified in any way. the secsi sector area can be protected using one of the following procedures: ? write the three-cycle enter secsi sector region command sequence, and then follow the in-system sector protect algorithm as shown in figure 2 , ex- cept that reset# may be at either v ih or v id . this allows in-system protec- tion of the secsi sector without raising any device pin to a high voltage. note that this method is only applicable to the secsi sector. secsi sector address range customer lockable esn factory locked custom factory locked 000000h?000007h determined by customer esn esn or determined by customer 000008h?00007fh unavailable determined by customer
96 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ? to verify the protect/unprotect status of the secsi sector, follow the algo- rithm shown in figure 3 . once the secsi sector is programmed, locked and verified, the system must write the exit secsi sector region command sequ ence to return to reading and writing within the remainder of the array. factory locked: secsi sector programmed and protected at the factory in devices with an esn, the secsi sector is protected when the device is shipped from the factory. the secsi sector cannot be modified in any way. an esn factory locked device has an 16-byte random esn at addresses 000000h?000007h. please contact your sales representative for details on ordering esn factory locked devices. customers may opt to have their code programmed by the factory through the spansion programming service (custom factory locked). the devices are then shipped from the factory with the secsi sector permanently locked. contact your sales representative for details on using the spansion programming service. write protect (wp#) the write protect function provides a hardware method of protecting the first or last sector group without using v id . write protect is one of two functions provided by the wp#/acc input. if the system asserts v il on the wp#/acc pin, the device disables program and erase functions in the first or last sector group independently of whether those sector groups were protected or unprotected using the method described in?ad- vanced sector protection? section on page 81. note that if wp#/acc is at v il when the device is in the standby mode, the maximum input load current is in- creased. see the table in ?dc characteristics? section on page 129. if the system asserts v ih on the wp#/acc pin, the device reverts to whether the first or last sector was previously set to be protected or un- protected using the method describe d in ?sector group protection and unprotection?. note that wp# has an internal pullup; when uncon- nected, wp# is at v ih . hardware data protection the command sequence requirement of unl ock cycles for programming or erasing provides data protection against inadvertent writes (refer to tables 16 and 17 for command definitions). in addition, the fo llowing hardware data protection mea- sures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during v cc power-up and power-down transitions, or from system noise. low v cc write inhibit when v cc is less than v lko , the device does not accept any write cycles. this pro- tects data during v cc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets to the read mode. subsequent writes are ignored until v cc is greater than v lko . the system must provide the proper signals to the control pins to prevent unintentional writes when v cc is greater than v lko .
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 97 preliminary write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe#, ce# or we# do not initiate a write cycle. logical inhibit write cycles are inhibited by holding any one of oe# = v il , ce# = v ih or we# = v ih . to initiate a write cycle, ce# and we# must be a logical zero while oe# is a logical one. power-up write inhibit if we# = ce# = v il and oe# = v ih during power up, the device does not accept commands on the rising edge of we#. the internal state machine is automatically reset to the read mode on power-up. common flash memory interface (cfi) the common flash interface (cfi) specification outlines device and host system software interrogation handshake, which allows specific vendor-specified soft- ware algorithms to be used for entire families of devices. software support can then be device-independent, jedec id -independent, and forward- and back- ward-compatible for the specified flas h device families. flash vendors can standardize their existing interfaces for long-term compatibility. this device enters the cfi query mode when the system writes the cfi query command, 98h, to address 55h, any time the device is ready to read array data. the system can read cfi information at the addresses given in tables 27- 30. to terminate reading cfi data, the system must write the reset command. the system can also write the cfi query command when the device is in the au- toselect mode. the device enters the cfi query mode, and the system can read cfi data at the addresses given in tables 27- 30. the system must write the reset command to return the device to reading array data. for further information, please refer to the cfi specification and cfi publication 100, available via the world wide web at http://www.amd.com/flash/cfi. alter- natively, contact your sales representative for copies of these documents.
98 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ta b l e 2 7 . cfi query identification string table 28. system interface string note: cfi data related to v cc and timeouts may differ from actual v cc and timeouts of the product. please consult the ordering information tables to obtain the vcc range for particular part numbers. please consult the erase and programming performance table for typical timeout specifications. addresses (x16) addresses (x8) data description 10h 11h 12h 20h 22h 24h 0051h 0052h 0059h query unique ascii string ?qry? 13h 14h 26h 28h 0002h 0000h primary oem command set 15h 16h 2ah 2ch 0040h 0000h address for primary extended table 17h 18h 2eh 30h 0000h 0000h alternate oem command set (00h = none exists) 19h 1ah 32h 34h 0000h 0000h address for alternate oem extended table (00h = none exists) addresses (x16) addresses (x8) data description 1bh 36h 0027h v cc min. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1ch 38h 0036h v cc max. (write/erase) d7?d4: volt, d3?d0: 100 millivolt 1dh 3ah 0000h v pp min. voltage (00h = no v pp pin present) 1eh 3ch 0000h v pp max. voltage (00h = no v pp pin present) 1fh 3eh 0007h reserved for future use 20h 40h 0007h typical timeout for min. size buffer write 2 n s (00h = not supported) 21h 42h 000ah typical timeout per individual block erase 2 n ms 22h 44h 0000h typical timeout for full chip erase 2 n ms (00h = not supported) 23h 46h 0001h reserved for future use 24h 48h 0005h max. timeout for buffer write 2 n times typical 25h 4ah 0004h max. timeout per individual block erase 2 n times typical 26h 4ch 0000h max. timeout for full chip erase 2 n times typical (00h = not supported)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 99 preliminary ta b l e 2 9 . device geometry definition addresses (x16) addresses (x8) data description 27h 4eh 0019h 0018h 0017h 0016h device size = 2 n byte 19 = 256 mb, 18 = 128 mb, 17 = 64 mb, 16 = 32 mb 28h 29h 50h 52h 0002h 0000h flash device interface description (refer to cfi publication 100) 2ah 2bh 54h 56h 0005h 0000h max. number of byte in multi-byte write = 2 n (00h = not supported) 2ch 58h 0001h 0002h number of erase block regions within device (01h = uniform device, 02h = boot device) 2dh 2eh 2fh 30h 5ah 5ch 5eh 60h 00xxh 000xh 00x0h 000xh erase block region 1 information (refer to the cfi specification or cfi publication 100) 003fh, 0000h, 0001h = 32 mb (-00, -03, -04) 007fh, 0000h, 0020h, 0000h = 32 mb (-01, -02), 64 mb (-01, -02) 007fh, 0000h, 0000h, 0001h = 64 mb (-00, -03, -04, -05, -06, -07) 00ffh, 0000h, 0000h, 0001h = 128 mb 00ffh, 0001h, 0000h, 0001h = 256 mb 31h 32h 33h 34h 60h 64h 66h 68h 00xxh 0000h 0000h 000xh erase block region 2 information (refer to cfi publication 100) 003eh, 0000h, 0000h, 0001h = 32 mb (-01, -02) 007eh, 0000h, 0000h, 0001h = 64 mb (-01, -02) 0000h, 0000h, 0000h, 0000h = all others 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information (refer to cfi publication 100) 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information (refer to cfi publication 100)
100 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ta b l e 3 0 . primary vendor-specific extended query addresses (x16) addresses (x8) data description 40h 41h 42h 80h 82h 84h 0050h 0052h 0049h query-unique ascii string ?pri? 43h 86h 0031h major version number, ascii 44h 88h 0033h minor version number, ascii 45h 8ah 0010h address sensitive unlock (bits 1-0) 0 = required, 1 = not required process technology (bits 7-2) 0010b = 0.23 m mirrorbit 46h 8ch 0002h erase suspend 0 = not supported, 1 = to read only, 2 = to read & write 47h 8eh 0001h sector protect 0 = not supported, x = number of sectors in per group 48h 90h 0000h sector temporary unprotect 00 = not supported, 01 = supported 49h 92h 0004h sector protect/unprotect scheme 0004h = standard mode (refer to text) 4ah 94h 0000h simultaneous operation 00 = not supported, x = number of sectors in bank 4bh 96h 0000h burst mode type 00 = not supported, 01 = supported 4ch 98h 0002h page mode type 00 = not supported, 01 = 4 word page, 02 = 8 word page 4dh 9ah 00b5h acc (acceleration) supply minimum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4eh 9ch 00c5h acc (acceleration) supply maximum 00h = not supported, d7-d4: volt, d3-d0: 100 mv 4fh 9eh 00xxh top/bottom boot sector flag 00h = uniform device without wp# protect, 02h = bottom boot device, 03h = top boot device, 04h = uniform sectors bottom wp# protect, 05h = uniform sectors top wp# protect 50h a0h 0001h program suspend 00h = not supported, 01h = supported
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 101 preliminary command definitions writing specific address and data commands or sequences into the command register initiates device operations. table 31 and table 32 define the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. a reset com- mand is then required to return the device to reading array data. all addresses are latched on the falling edge of we# or ce#, whichever happens later. all data is latched on the rising edge of we# or ce#, whichever happens first. refer to the ac characteri stics section for timing diagrams. reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is ready to read array data after completing an embedded program or embedded erase algorithm. after the device accepts an erase suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non- erase-suspended sector. after completing a programming operation in the erase suspend mode, the system may once again read array data with the same ex- ception. see the erase suspend/erase resume commands section for more information. the system must issue the reset command to return the device to the read (or erase-suspend-read) mode if dq5 goes high during an active program or erase operation, or if the device is in the autoselect mode. see the next section, reset command, for more information. see also requirements for reading array data in the device bus operations sec- tion for more information. the read-only operations??ac characteristics? section on page 122 provides the read parameters, and figure 12 shows the tim- ing diagram. reset command writing the reset command resets the device to the read or erase-suspend-read mode. address bits are don?t cares for this command. the reset command may be written between the sequence cycles in an erase command sequence before erasing begins. this resets the device to the read mode. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the sequence cycles in a program command sequence before programming begins. this resets the device to the read mode. if the program command sequen ce is written while the device is in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode. once programming begins, however, the device ig- nores reset commands until the operation is complete. the reset command may be written between the sequence cycles in an autoselect command sequence. once in the autoselect mode, the reset command must be written to return to the read mode. if the device entered the autoselect mode while in the erase suspend mode, writing the reset command returns the device to the erase-suspend-read mode.
102 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary if dq5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in erase suspend). note that if dq1 goes high during a wr ite buffer programming operation, the sys- tem must write the write-to-buffer-abort reset command sequence to reset the device for the next operation. autoselect command sequence the autoselect command sequence allows the host system to read several iden- tifier codes at specific addresses: note: the device id is read over three cycles. sa = sector address the autoselect command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle that contains the autoselect command. the device then enters the autoselect mode. the system may read at any address any number of times without initiating another autoselect command sequence: the system must write the reset command to return to the read mode (or erase- suspend-read mode if the device was previously in erase suspend). enter secsi sector/exit secsi sector command sequence the secsi sector region provides a secured data area containing an 8-word/16- byte random electronic serial number (esn). the system can access the secsi sector region by issuing the three-cycle enter secsi sector command sequence. the device continues to access the secsi sector region until the system issues the four-cycle exit secsi sector command sequence. the exit secsi sector com- mand sequence returns the device to normal operation. table 31 and table 32 show the address and data requirements for both command sequences. see also ?secsi (secured silicon) sector flash memory region? for further information. note that the acc function and unlock bypass modes are not available when the secsi sector is enabled. write buffer programming write buffer programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. this results in faster effective programming time than the standard programming algorithms. the write buffer programming command sequence is initiated by first writing two unlock cycles. this is followed by a third write cycle containing the write buffer load command written at the sector address in which programming will occur. the fourth cycle writes the sec- tor address and the number of word locations, minus one, to be programmed. for example, if the system will program 6 uni que address locations, then 05h should be written to the device. this tells the device how many write buffer addresses will be loaded with data and therefore when to expect the program buffer to flash identifier code a7:a0 (x16) a6:a-1 (x8) manufacturer id 00h 00h device id, cycle 1 01h 02h device id, cycle 2 0eh 1ch device id, cycle 3 0fh 1eh secsi sector factory protect 03h 06h sector protect verify (sa)02h (sa)04h
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 103 preliminary command. the number of locations to program cannot exceed the size of the write buffer or the operation will abort. the fifth cycle writes the first address location and data to be programmed. the write-buffer-page is selected by address bits a max ?a 4 . all subsequent address/ data pairs must fall within the selected-write-buffer-page. the system then writes the remaining address/data pairs into the write buffer. write buffer loca- tions may be loaded in any order. the write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (this means write buffer programming cannot be performed across multiple write-buffer pages. this also means that write buffer program- ming cannot be performed across multiple sectors. if the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. note that if a write buffer address location is loaded multiple times, the address/ data pair counter will be decremented for every data load operation. the host system must therefore account for loading a write-buffer location more than once. the counter decrements for each data load operation, not for each unique write-buffer-address location. note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. once the specified number of write buffer locations have been loaded, the system must then write the program buffer to flash command at the sector address. any other address and data combination aborts the write buffer programming oper- ation. the device then begins programming. data polling should be used while monitoring the last address location loaded into the write buffer. dq7, dq6, dq5, and dq1 should be monitored to determine the device status during write buffer programming. the write-buffer programming operation can be suspended using the standard program suspend/resume commands. upon successful completion of the write buffer programming operation, the device is ready to execute the next command. the write buffer programming sequence ca n be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program step. ? write to an address in a sector different than the one specified during the write-buffer-load command. ? write an address/data pair to a different write-buffer-page than the one se- lected by the starting address during the write buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = data# (for the last address location loaded), dq6 = toggle, and dq5=0. a write-to-buffer-abort reset com- mand sequence must be written to reset the device for the next operation. note that the secsi sector, autoselect, and cfi functions are unavailable when a program operation is in progress. a bit cannot be programmed from ?0? back to a ?1.? attempting to do so may cause the device to set dq5 = 1, or cause the dq7 and dq6 status bits to indicate the operation was success- ful. however, a succeeding read will show that the data is still ?0.? only erase operations can convert a ?0? to a ?1.?
104 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary accelerated program the device offers accelerated program operations through the wp#/acc or acc pin, depending on the particular product. by asserting v hh on the wp#/acc or acc pin, the device uses the higher voltage on the wp#/acc pin to accelerate the operation. note that the wp#/ acc pin must not be at v hh for operations other than accelerated programming, or device damage may result. wp# has an internal pullup; when unconnected, wp# is at v ih . figure 1 illustrates the algorithm for the program operation. refer to the erase and program operations??ac characteristics? section on page 122 section for pa- rameters, and ?read operation timings? section on page 124 for timing diagrams.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 105 preliminary figure 3. write buffer programming operation write ?write to buffer? command and sector address write program buffer to flash sector address write first address/data to buffer fail or abort pass read dq15 - dq0 at last loaded address read dq15 - dq0 with address = last loaded address write next address/data to buffer part of ?write to buffer? command sequence ye s ye s ye s ye s ye s no no no no no no 16th word of data written? dq7 and dq15 = data? dq7 and dq15 = data? dq5 and dq13 = 1? dq1 = 1? write to buffer aborted. must write ?write-to-buffer abort reset? command sequence to return to read mode. ye s abort write to buffer operation? notes: 1. when sector address is specified, any address in the selected sector is acceptable. however, when loading write-buffer address locations with data, all addresses must fall within the selected write-buffer page. 2. dq7 may change simultaneously with dq5. therefore, dq7 should be verified. 3. if this flowchart location was reached because dq5= ?1?, then the device failed. if this flowchart location was reached because dq1= ?1?, then the write to buffer operation was aborted. in either case, the proper reset command must be written before the device can begin another operation. if dq1=1, write the write- buffer-programming-abort-reset command. if dq5=1, write the reset command. 4. see tables 16 and 17 for command sequences required for write buffer programming. (
106 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary program suspend/prog ram resume command sequence the program suspend command allows the system to interrupt a write-to-buffer programming operation so that data can be read from any non-suspended sector. when the program suspend command is written during a programming process, the device halts the program operation within 15 s maximum (5 s typical) and updates the status bits. addresses are not required when writing the program suspend command. after the programming operation has been suspended, the system can read array data from any non-suspended sector. the program suspend command may also be issued during a programming operation while an erase is suspended. in this case, data may be read from any addresses not in erase suspend or program suspend. if a read is needed from the secsi sector area (one-time program area), then user must use the proper co mmand sequences to enter and exit this region. note that the secsi sector, autoselect, and cfi functions are un- available when a program operation is in progress. the system may also write the autoselect command sequence when the device is in the program suspend mode. the system can read as many autoselect codes as required. when the device exits the autoselect mode, the device reverts to the program suspend mode, and is ready for another valid operation. see autoselect command sequence for more information. after the program resume command is written, the device reverts to program- ming. the system can determine the status of the program operation using the dq7 or dq6 status bits, just as in the standard program operation. see write op- eration status for more information. the system must write the program resume command (address bits are don?t care) to exit the program suspend mode and continue the programming opera- tion. further writes of the resume command are ignored. another program suspend command can be written after the device has resumed programming.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 107 preliminary figure 4. program suspend/program resume chip erase command sequence chip erase is a six bus cycle operation. the chip erase command sequence is ini- tiated by writing two unlock cycles, followed by a set-up command. two additional unlock write cycles are then followed by the chip erase command, which in turn invokes the embedded erase algorithm. the device does not require the system to preprogram prior to erase. the embedded erase algorithm auto- matically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or tim- ings during these operations. tables 31- and tables 32- show the address and data requirements for the chip erase command sequence. when the embedded erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. the system can determine the status of the erase operation by using dq7, dq6, or dq2. refer to the write operation status section for information on these status bits. any commands written during the chip erase operation are ignored. however, note that a hardware reset immediately terminates the erase operation. if that occurs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 section for timing diagrams. write-to-buffer sequence in progress write program suspend command sequence command is also valid for erase-suspended-program operations autoselect and secsi sector read operations are also allowed data cannot be read from erase- o r program-suspended sectors write program resume command sequence read data as required done reading? no yes write address/data xxxh/30h device reverts to operation prior to program suspend write address/data xxxh/b0h wait 15 s
108 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary sector erase command sequence sector erase is a six bus cycle operation. the sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. two addi- tional unlock cycles are written, and are then followed by the address of the sector to be erased, and the sector erase command. tables 31- and tables 32- shows the address and data requirements for the sector erase command sequence. the device does not require the system to preprogram prior to erase. the em- bedded erase algorithm automatically prog rams and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. after the command sequence is written, a sector erase time-out of 50 s occurs. during the time-out period, additional sector addresses and sector erase com- mands may be written. loading the sector erase buffer may be done in any sequence, and the number of sectors may be from one sector to all sectors. the time between these additional cycles must be less than 50 s, otherwise erasure may begin. any sector erase address and command following the exceeded time- out may or may not be accepted. it is recommended that processor interrupts be disabled during this time to ensure al l commands are accepted. the interrupts can be re-enabled after the last sector erase command is written. any com- mand other than sector erase or erase suspend during the time-out period resets the device to the read mode. note that the secsi sector, autoselect, and cfi functions are unavailable when an erase operation is in progress. the system must rewrite the command sequence and any addi- tional addresses and commands. the system can monitor dq3 to determine if the sector erase timer has timed out (see the section on dq3: sector erase timer.). the time-out begins from the ris- ing edge of the final we# pulse in the command sequence. when the embedded erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. the system can determine the status of the erase operation by reading dq7, dq6, or dq2 in the erasing sector. refer to the write operation status section for information on these status bits. once the sector erase operation has begun, only the erase suspend command is valid. all other commands are ignored. however, note that a hardware reset im- mediately terminates the erase operation. if that occurs, the sector erase command sequence should be reinitiated on ce the device has returned to reading array data, to ensure data integrity. figure 5 illustrates the algorithm for the erase operation. refer to the erase and program operations table in the ac characteristics section for parameters, and figure 17 section for timing diagrams.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 109 preliminary figure 5. erase operation erase suspend/erase resume commands the erase suspend command, b0h, allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. this command is valid only during the sector erase operation, includ- ing the 50 s time-out period during the sector erase command sequence. the erase suspend command is ignored if written during the chip erase operation or embedded program algorithm. when the erase suspend command is written during the sector erase operation, the device requires a typical of 5 s ( maximum of 20 s) to suspend the erase operation. however, when the erase suspend command is written during the sec- tor erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after the erase operation has been suspended, the device enters the erase-sus- pend-read mode. the system can read data from or program data to any sector not selected for erasure. (the device ?erase suspends? all sectors selected for erasure.) reading at any address within erase-suspended sectors produces sta- tus information on dq7?dq0. the system can use dq7, or dq6 and dq2 together, to determine if a sector is actively erasing or is erase-suspended. refer to the write operation status section for information on these status bits. after an erase-suspended program operation is complete, the device returns to the erase-suspend-read mode. the system can determine the status of the pro- start write erase command sequence (notes 1, 2) data poll to erasing bank from system data = ffh? no yes erasure completed embedded erase algorithm in progress notes: 1. see table 31 and table 32 for erase command sequence. 2. see the section on dq3 for information on the sector erase timer.
110 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary gram operation using the dq7 or dq6 status bits, just as in the standard word program operation. refer to the write operation status section for more information. in the erase-suspend-read mode, the system can also issue the autoselect com- mand sequence. refer to the ?autoselect mode? section on page 77 and ?autoselect command sequence? section on page 102 sections for details. to resume the sector erase operation, the system must write the erase resume command. further writes of the resume command are ignored. another erase suspend command can be written after the chip has resumed erasing.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 111 preliminary command definitions table 31. command definitions (x16 mode, byte# = v ih ) command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 5) 1 ra rd reset (note 6) 1 xxx f0 autoselect (note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 0001 device id (note 8) 6 555 aa 2aa 55 555 90 x01 227e x0e note 15 x0f note 15 secsi ? sector factory protect (note 9) 4 555 aa 2aa 55 555 90 x03 (note 10) sector group protect verify (note 10) 4 555 aa 2aa 55 555 90 (sa)x02 00/01 enter secsi sector region 3 555 aa 2aa 55 555 88 exit secsi sector region 4 555 aa 2aa 55 555 90 xxx 00 write to buffer 20 555 aa 2aa 55 sa 25 sa 0f pba pbd program buffer to flash 1 sa 29 write to buffer abort reset (note 11) 3 555 aa 2aa 55 555 f0 chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 sector erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 sa 30 program/erase suspend (note 12) 1 xxx b0 program/erase resume (note 13) 1 xxx 30 cfi query (note 14) 1 55 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pba = program buffer address . addresses latch on falling edge of we# or ce# pulse, whichever happens later. pbd = program buffer data for location pba. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or 2aa as shown in table, address bits above a11 and data bits above dq7 are don?t care. 5. no unlock or command cycles required when device is in read mode. 6. reset command is required to return to read mode (or to erase- suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 7. fourth cycle of the autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. except for rd, pd and wc. see autoselect command sequence section for more information. 8. device id must be read in three cycles. 9. if wp# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. if wp# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. 10. data is 00h for an unprotected sector group and 01h for a protected sector group. 11. command sequence resets device for next command after aborted write-to-buffer operation. 12. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 13. erase resume command is valid only during erase suspend mode. 14. command is valid when device is ready to read array data or when device is in autoselect mode. 15. refer to table 14, autoselect codes for individual device ids per device density and model number.
112 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary table 32. command definitions (x8 mode, byte# = v il ) command sequence (note 1) cycles bus cycles (notes 2?5) first second third fourth fifth sixth addr data addr data addr data addr data addr data addr data read (note 6) 1 ra rd reset (note 7) 1 xxx f0 autoselect (note 8) manufacturer id 4 aaa aa 555 55 aaa 90 x00 01 device id (note 9) 6 aaa aa 555 55 aaa 90 x02 7e x1c note 16 x1e note 16 secsi ? sector factory protect (note 10) 4 aaa aa 555 55 aaa 90 x06 (note 10) sector group protect verify (note 11) 4 aaa aa 555 55 aaa 90 (sa)x04 00/01 enter secsi sector region 3 aaa aa 555 55 aaa 88 exit secsi sector region 4 aaa aa 555 55 aaa 90 xxx 00 write to buffer 36 aaa aa 555 55 sa 25 sa 1f pba pbd program buffer to flash 1 sa 29 write to buffer abort reset (note 12) 3 aaa aa 555 55 aaa f0 chip erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 sector erase 6 aaa aa 555 55 aaa 80 aaa aa 555 55 sa 30 program/erase suspend (note 13) 1 xxx b0 program/erase resume (note 14) 1 xxx 30 cfi query (note 15) 1 aa 98 legend: x = don?t care ra = read address of memory location to be read. rd = read data read from location ra during read operation. pba = program buffer address . addresses latch on falling edge of we# or ce# pulse, whichever happens later. pbd = program buffer data for location pba. data latches on rising edge of we# or ce# pulse, whichever happens first. sa = sector address of sector to be verified (in autoselect mode) or erased. address bits a21?a15 uniquely select any sector. notes: 1. see table 1 for description of bus operations. 2. all values are in hexadecimal. 3. shaded cells indicate read cycles. all others are write cycles. 4. during unlock and command cycles, when lower address bits are 555 or aaa as shown in table, address bits above a11 are don?t care. 5. unless otherwise noted, address bits a21?a11 are don?t cares. 6. no unlock or command cycles required when device is in read mode. 7. reset command is required to return to read mode (or to erase- suspend-read mode if previously in erase suspend) when device is in autoselect mode, or if dq5 goes high while device is providing status information. 8. fourth cycle of autoselect command sequence is a read cycle. data bits dq15?dq8 are don?t care. see autoselect command sequence section or more information. 9. device id must be read in three cycles. 10. if wp# protects highest address sector, data is 98h for factory locked and 18h for not factory locked. if wp# protects lowest address sector, data is 88h for factory locked and 08h for not factor locked. 11. data is 00h for an unprotected sector group and 01h for a protected sector group. 12. command sequence resets device for next command after aborted write-to-buffer operation. 13. system may read and program in non-erasing sectors, or enter autoselect mode, when in erase suspend mode. erase suspend command is valid only during a sector erase operation. 14. erase resume command is valid only during erase suspend mode. 15. command is valid when device is ready to read array data or when device is in autoselect mode. 16. refer to table 14, autoselect codes for individual device ids per device density and model number.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 113 preliminary write operation status the device provides several bits to determine the status of a program or erase operation: dq2, dq3, dq5, dq6, and dq7. table 19 and the following subsec- tions describe the function of these bits. dq7 and dq6 each offer a method for determining whether a program or erase operation is complete or in progress. the device also provides a hardware-based output signal, ry/by#, to determine whether an embedded program or erase operation is in progress or has been completed. dq7: data# polling the data# polling bit, dq7, indicates to the host system whether an embedded program or erase algorithm is in progress or completed, or whether the device is in erase suspend. data# polling is valid after the rising edge of the final we# pulse in the command sequence. during the embedded program algorithm, the device outputs on dq7 the com- plement of the datum programmed to dq7. this dq7 status also applies to programming during erase suspend. when the embedded program algorithm is complete, the device outputs the datum programmed to dq7. the system must provide the program address to read valid status information on dq7. if a pro- gram address falls within a protected sector, data# polling on dq7 is active for approximately 1 s, then the device returns to the read mode. during the embedded erase algorithm, data# polling produces a ?0? on dq7. when the embedded erase algorithm is complete, or if the device enters the erase suspend mode, data# polling produces a ?1? on dq7. the system must provide an address within any of the sectors selected for erasure to read valid status information on dq7. after an erase command sequence is written, if all sectors selected for erasing are protected, data# polling on dq7 is active for approximately 100 s, then the device returns to the read mode. if not all selected sectors are protected, the em- bedded erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. however, if the system reads dq7 at an address within a protected sector, the status may not be valid. just prior to the completion of an embedded program or erase operation, dq7 may change asynchronously with dq0?dq6 while output enable (oe#) is as- serted low. that is, the device may change from providing status information to valid data on dq7. depending on when the system samples the dq7 output, it may read the status or valid data. even if the device has completed the program or erase operation and dq7 has valid data, the data outputs on dq0?dq6 may be still invalid. valid data on dq0?dq7 will appear on successive read cycles. ta b l e s 33- shows the outputs for data# polling on dq7. figure 6 shows the data# polling algorithm. figure 17 in the ac characteristics section shows the data# polling timing diagram.
114 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary figure 6. data# polling algorithm ry / b y # : r e a d y / bu s y # the ry/by# is a dedicated, open-drain output pin which indicates whether an embedded algorithm is in progress or complete. the ry/by# status is valid after the rising edge of the final we# pulse in the command sequence. since ry/by# is an open-drain output, several ry/by# pins can be tied together in parallel with a pull-up resistor to v cc . if the output is low (busy), the device is actively erasing or programming. (this includes programming in the erase suspend mode.) if the output is high (ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. tables 33- shows the outputs for ry/by#. dq7 and dq15 = data? yes no no dq5 and dq13 = 1? no yes yes fail pass read dq15?dq0 addr = va read dq15?dq0 addr = va dq7 and dq15 = data? start notes: 1. va = valid address for programming. during a sector erase operation, a valid address is any sector address within the sector being erased. during chip erase, a valid address is any non-protected sector address. 2. dq7 should be rechecked even if dq5 = ?1? because dq7 may change simultaneously with dq5.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 115 preliminary dq6: toggle bit i toggle bit i on dq6 indicates whether an embedded program or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. during an embedded program or erase algorithm operation, successive read cy- cles to any address cause dq6 to toggle. the system may use either oe# or ce# to control the read cycles. when the operation is complete, dq6 stops toggling. after an erase command sequence is written, if all sectors selected for erasing are protected, dq6 toggles for approximately 100 s, then returns to reading array data. if not all selected sectors are protected, the embedded erase algo- rithm erases the unprotected sectors, and ignores the selected sectors that are protected. the system can use dq6 and dq2 together to determine whether a sector is ac- tively erasing or is erase-suspended. when the device is actively erasing (that is, the embedded erase algorithm is in progress), dq6 toggles. when the device en- ters the erase suspend mode, dq6 stops toggling. however, the system must also use dq2 to determine which sectors are erasing or erase-suspended. alter- natively, the system can use dq7 (see the subsection on dq7: data# polling). if a program address falls within a protected sector, dq6 toggles for approxi- mately 1 s after the program command sequence is written, then returns to reading array data. dq6 also toggles during the erase-suspend-program mode, and stops toggling once the embedded program algorithm is complete. ta b l e s 33- shows the outputs for toggle bit i on dq6. figure 7 shows the toggle bit algorithm. figure 19 in the ?ac characteristics? section shows the toggle bit timing diagrams. figure 20 shows the differences between dq2 and dq6 in graphical form. see also the subsection on dq2: toggle bit ii.
116 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary figure 7. toggle bit algorithm dq2: toggle bit ii the ?toggle bit ii? on dq2, when used with dq6, indicates whether a particular sector is actively erasing (that is, the embedded erase algorithm is in progress), or whether that sector is erase-suspended. toggle bit ii is valid after the rising edge of the final we# pulse in the command sequence. start no yes yes dq5 = 1? no yes toggle bit = toggle? no program/erase operation not complete, write reset command program/erase operation complete read dq7?dq0 toggle bit = toggle? read dq7?dq0 twice read dq7?dq0 note: the system should recheck the toggle bit even if dq5 = ?1? because the toggle bit may stop toggling as dq5 changes to ?1.? see the subsections on dq6 and dq2 for more information.
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 117 preliminary dq2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe# or ce# to control the read cycles.) but dq2 cannot distinguish whether the sector is actively erasing or is erase-suspended. dq6, by comparison, indicates whether the device is actively erasing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sector and mode information. refer to tables 33- to compare outputs for dq2 and dq6. figure 7 shows the toggle bit algorithm in flowchart form, and the section ?dq2: toggle bit ii? explains the algorithm. see also the ry/by#: ready/busy# subsec- tion. figure 19 shows the toggle bit timing diagram. figure 20 shows the differences between dq2 and dq6 in graphical form. reading toggle bits dq6/dq2 refer to figure 7 for the following discussion. whenever the system initially be- gins reading toggle bit status, it must read dq7?dq0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on dq 7?dq0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of dq5 is high (see the section on dq5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as dq5 went high. if the toggle bit is no longer toggling, the device has suc- cessfully completed the program or erase operation. if it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that the system initially determines that the toggle bit is toggling and dq5 has not gone high. the system may continue to monitor the toggle bit and dq5 through successive read cycles, determining the status as de- scribed in the previous paragraph. altern atively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algo- rithm when it returns to determine the status of the operation (top of figure 6). dq5: exceeded timing limits dq5 indicates whether the program, erase, or write-to-buffer time has ex- ceeded a specified internal pulse count limit. under these conditions dq5 produces a ?1,? indicating that the program or erase cycle was not successfully completed. the device may output a ?1? on dq5 if the system tries to program a ?1? to a location that was previously programmed to ?0.? only an erase operation can change a ?0? back to a ?1.? under this condition, the device halts the opera- tion, and when the timing limit has been exceeded, dq5 produces a ?1.? in all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). dq3: sector erase timer after writing a sector erase command sequence, the system may read dq3 to de- termine whether or not erasure has begun. (the sector erase timer does not
118 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary apply to the chip erase command.) if additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. when the time-out period is complete, dq3 switches from a ?0? to a ?1.? if the time between additional sector erase commands from the system can be as- sumed to be less than 50 s, the system need not monitor dq3. see also the sector erase command sequence section. after the sector erase command is written, the system should read the status of dq7 (data# polling) or dq6 (toggle bit i) to ensure that the device has accepted the command sequence, and then read dq3. if dq3 is ?1,? the embedded erase algorithm has begun; all further commands (except erase suspend) are ignored until the erase operation is complete. if dq3 is ?0,? the device will accept addi- tional sector erase commands. to ensu re the command has been accepted, the system software should check the status of dq3 prior to and following each sub- sequent sector erase command. if dq3 is high on the second status check, the last command might not have been accepted. ta b l e s 33- shows the status of dq3 relative to the other status bits. dq1: write-to-buffer abort dq1 indicates whether a write-to-buffer operation was aborted. under these conditions dq1 produces a ?1?. the system must issue the write-to-buffer-abort- reset command sequence to return the de vice to reading array data. see write buffersection for more details. table 33. write operation status notes: 1. dq5 switches to ?1? when an embedded program, embedded erase, or write-to-buffer operation has exceeded the maximum timing limits. refer to the section on dq5 for more information. 2. dq7 and dq2 require a valid address when reading status information. refer to the appropriate subsection for further details. 3. the data# polling algorithm should be used to monitor the last loaded write-buffer address location. 4. dq1 switches to ?1? when the device has aborted the write-to-buffer operation status dq7 (note 2) dq6 dq5 (note 1) dq3 dq2 (note 2) dq1 ry/by# standard mode embedded program algorithm dq7# toggle 0 n/a no toggle 0 0 embedded erase algorithm 0 toggle 0 1 toggle n/a 0 program suspend mode program- suspend read program-suspended sector invalid (not allowed) 1 non-program suspended sector data 1 erase suspend mode erase- suspend read erase-suspended sector 1 no toggle 0 n/a toggle n/a 1 non-erase suspended sector data 1 erase-suspend-program (embedded program) dq7# toggle 0 n/a n/a n/a 0 write-to- buffer busy (note 3) dq7# toggle 0 n/a n/a 0 0 abort (note 4) dq7# toggle 0 n/a n/a 1 0
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 119 preliminary absolute maximum ratings storage temperature, plastic packages . . . . . . . . . . . . . . . . ?65c to +150c ambient temperature with power applied . . . . . . . . . . . . . . ?65c to +125c voltage with respect to ground: v cc (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.5 v to +4.0 v a9, oe#, acc and reset# (note 2) . . . . . . . . . . . . . ?0.5 v to +12.5 v all other pins (note 1) . . . . . . . . . . . . . . . . . . . . ?0.5 v to v cc +12.5 v output short circuit current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/os is ?0.5 v. during voltage transitions, inputs or i/os may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8 . maximum dc voltage on input or i/os is v cc + 0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc + 2.0 v for periods up to 20 ns. see figure 9 . 2. minimum dc input voltage on pins a9, oe#, acc, and reset# is ?0.5 v. during voltage transitions, a9, oe#, acc, and reset# may overshoot v ss to ?2.0 v for periods of up to 20 ns. see figure 8 . maximum dc input voltage on pin a9, oe#, acc, and reset# is +12.5 v which may overshoot to +14.0v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . . . . . . . . . . . . . . . . . ?40c to +85c supply voltages v cc for full voltage range . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 v to +3.6 v v cc for regulated voltage range . . . . . . . . . . . . . . . . . . . . . +3.0 v to +3.6 v notes: 1. operating ranges define those limits between which the functionality of the device is guaranteed. figure 8. maximum negative overshoot waveform figure 9. maximum positive overshoot waveform 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns v cc +2.0 v v cc +0.5 v 20 ns 2.0 v
120 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary dc characteristics cmos compatible notes: 1. on the wp#/acc pin only, the maximu m input load current when wp# = v il is 2.0 a. 2. the i cc current listed is typically less than 2 ma/mhz, with oe# at v ih . 3. maximum i cc specifications are tested with v cc = v cc max. 4. s29gl032m, s29gl064m 5. s29gl128m, s29gl256m 6. i cc active while embedded erase or embedded program is in progress. 7. automatic sleep mode enables the low power mode when addresses remain stable for t acc + 30 ns. 8. v cc voltage requirements. 9. not 100% tested. parameter symbol parameter description (notes) test conditions min typ max unit i li input load current ((1)) v in = v ss to v cc , v cc = v cc max 1.0 a i lit a9, acc input load current v cc = v cc max ; a9 = 12.5 v 35 a i lr reset leakage current v cc = v cc max ; reset# = 12.5 v 35 a i lo output leakage current v out = v ss to v cc , v cc = v cc max 1.0 a i cc1 v cc initial page read current ((2), (3)) ce# = v il, oe# = v ih 1 mhz 5 20 ma 5 mhz (4) 18 25 5 mhz (5) 25 35 10 mhz (4) 35 50 10 mhz (5) 40 60 i cc2 v cc intra-page read current ((2), (3)) ce# = v il, oe# = v ih 10 mhz 5 20 ma 40 mhz 10 40 i cc3 v cc active write current ((3), (4)) ce# = v il, oe# = v ih 50 60 ma i cc4 v cc standby current ((3)) ce#, reset# = v cc 0.3 v, wp# = v ih 15a i cc5 v cc reset current ((3)) reset# = v ss 0.3 v, wp# = v ih 15a i cc6 automatic sleep mode ((3), (7)) v ih = v cc 0.3 v; v il = v ss 0.3 v, wp# = v ih 15a v il1 input low voltage 1((8)) ?0.5 0.8 v v ih1 input high voltage 1 ((8)) 0.7 v cc v cc + 0.5 v v hh voltage for acc program acceleration v cc = 2.7 ?3.6 v 11.5 12.0 12.5 v v id voltage for autoselect and temporary sector unprotect v cc = 2.7 ?3.6 v 11.5 12.0 12.5 v v ol output low voltage ((8)) i ol = 4.0 ma, v cc = v cc min 0.15 v cc v v oh1 output high voltage i oh = ?2.0 ma, v cc = v cc min 0.85 v cc v v oh2 i oh = ?100 a, v cc = v cc min v cc ?0.4 v v lko low v cc lock-out voltage ((9)) 2.3 2.5 v
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 121 preliminary test conditions key to switching waveforms figure 11. input waveforms and measurement levels note: diodes are in3064 or equivalent figure 10. test setup table 34. test specifications 2.7 k ? c l 6.2 k ? 3.3 v device under test test condition all speeds unit output load 1 ttl gate output load capacitance, c l (including jig capacitance) 30 pf input rise and fall times 5 ns input pulse levels 0.0 or v cc v input timing measurement reference levels (see note) 0.5 v cc v output timing measurement reference levels 0.5 v cc v waveform inputs outputs steady changing from h to l changing from l to h don?t care, any change permitted changing, state unknown does not apply center line is high impedance state (high z)
122 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics read-only operations-s29gl256m only notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. read-only operations-s29gl128m only notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. parameter description test setup speed options unit jedec std. 10 11 t avav t rc read cycle time (note 1) min 100 100 ns t avqv t acc address to output delay ce#, oe# = v il max 100 100 ns t elqv t ce chip enable to output delay oe# = v il max 100 100 ns t pacc page access time max 30 30 ns t glqv t oe output enable to output delay max 30 30 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns parameter description test setup speed options unit jedec std. 90 10 t avav t rc read cycle time (note 1) min 90 100 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 ns t pacc page access time max 25 30 ns t glqv t oe output enable to output delay max 25 30 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh output hold time from addresses, ce# or oe#, whichever occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns tog gl e a n d data# polling min 10 ns
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 123 preliminary ac characteristics read-only operations-s29gl064m only notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. read-only operations-s29gl032m only notes: 1. not 100% tested. 2. see figure 12 and table 13 for test specifications. parameter description test setup speed options unit jedec std. 90 10 11 t avav t rc read cycle time (note 1) min 90 100 110 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 ns t pacc page access time max 25 30 30 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh o u t p u t h o l d t i m e f r o m a d d re s s e s , c e # o r o e# , w h i c h e v e r occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns parameter description test setup speed options unit jedec std. 90 10 11 t avav t rc read cycle time (note 1) min 90 100 110 ns t avqv t acc address to output delay ce#, oe# = v il max 90 100 110 ns t elqv t ce chip enable to output delay oe# = v il max 90 100 110 ns t pacc page access time max 25 30 30 ns t glqv t oe output enable to output delay max 25 30 30 ns t ehqz t df chip enable to output high z (note 1) max 16 ns t ghqz t df output enable to output high z (note 1) max 16 ns t axqx t oh o u t p u t h o l d t i m e f r o m a d d re s s e s , c e # o r o e # , w h i c h e v e r occurs first min 0 ns t oeh output enable hold time (note 1) read min 0 ns toggle and data# polling min 10 ns
124 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics figure 12. read operation timings * figure shows device in word mode. addresses are a1?a-1 for byte mode. figure 13. page read timings t oh t ce outputs we# addresses ce# oe# high z output valid high z addresses stable t rc t acc t oeh t rh t oe t rh 0 v ry/by# reset# t df a23 - a2 ce# oe# a1 - a0* data bus same page aa ab ac ad qa qb qc qd t acc t pac c t pac c t pac c
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 125 preliminary ac characteristics hardware reset (reset#) notes: 1. not 100% tested. figure 14. reset timings parameter description all speed options unit jedec std. t ready reset# pin low (during embedded algorithms) to read mode (see note) max 20 s t ready reset# pin low (not during embedded algorithms) to read mode (see note) max 500 ns t rp reset# pulse width min 500 ns t rh reset high time before read (see note) min 50 ns t rpd reset# input low to standby mode (see note) min 20 s t rb ry/by# output high to ce#, oe# pin low min 0 ns reset# ry/by# ry/by# t rp t ready reset timings not during embedded algorithms t ready ce#, oe# t rh ce#, oe# reset timings during embedded algorithms reset# t rp t rb
126 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics erase and program operations-s29gl256m only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 10 11 t avav t wc write cycle time (note 1) min 100 110 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling mm 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 100 110 ns t poll program valid before status polling (note 6) max 4 ns
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 127 preliminary ac characteristics erase and program operations-s29gl128m only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 90 10 t avav t wc write cycle time (note 1) min 90 100 ns t avwl t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 45 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling mm 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 90 100 ns t poll program valid before status polling (note 5) max 4 ns
128 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics erase and program operations-s29gl064m only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 90 10 11 t avav t wc write cycle time (note 1) min 90 100 110 ns t avw l t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling mm 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 90 100 110 ns t poll program valid before status polling (note 5) max 4 ns
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 129 preliminary ac characteristics erase and program operations-s29gl032m only notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 90 10 11 t avav t wc write cycle time (note 1) min 90 100 110 ns t avw l t as address setup time min 0 ns t aso address setup time to oe# low during toggle bit polling min 15 ns t wlax t ah address hold time min 45 ns t aht address hold time from ce# or oe# high during toggle bit polling min 0 ns t dvwh t ds data setup time min 35 ns t whdx t dh data hold time min 0 ns t ceph ce# high during toggle bit polling mm 20 ns t oeph oe# high during toggle bit polling min 20 ns t ghwl t ghwl read recovery time before write (oe# high to we# low) min 0 ns t elwl t cs ce# setup time min 0 ns t wheh t ch ce# hold time min 0 ns t wlwh t wp write pulse width min 35 ns t whdl t wph write pulse width high min 30 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 s effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t vhh v hh rise and fall time (note 1) min 250 ns t vcs v cc setup time (note 1) min 50 s t busy we# high to ry/by# low min 90 100 110 ns t poll program valid before status polling (note 5) max 4 ns
130 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics notes: 1. left side of figure indicates last cycle of a write-to-buffer operation followed by the program buffer to flash command. 2. pba = program buffer address, pbd = program buffer data, sa= sector address, d out is the true data at the program address. 3. illustration shows device in word mode. figure 15. program operation timings figure 16. accelerated program timing diagram oe# we# ce# v cc data addresses t ds t ah t dh t wp 29 t whwh1 t wc t as t wph t vcs pba sa pa read status data (last two cycles) pbd t poll t cs status d out ry/by# t rb t busy t ch pa acc t vhh v hh v il or v ih v il or v ih t vhh
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 131 preliminary ac characteristics notes: 1. sa = sector address (for sector erase), va = valid addres s for reading status data (see ?write operation status?. 2. illustration shows device in word mode. figure 17. chip/sector erase operation timings oe# ce# addresses v cc we# data 2aah sa t ah t wp t wc t as t wph 555h for chip erase 10 for chip erase 3030h t ds t vcs t cs t dh 5555h t ch in progress complete t whwh2 va va erase command sequence (last two cycles) read status data ry/by# t rb t busy
132 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics note: va = valid address. illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle. figure 18. data# polling timings (during embedded algorithms) we# ce# oe# hig h t oe hig h dq7 dq0?dq6 ry/by# t busy complement tr u e addresses va t ch va va status data complement status data tr u e valid data valid data t rc t oeh t ce t oh t df t acc t poll
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 133 preliminary ac characteristics note: va = valid address; not required for dq6. illustration shows first two status cycle after command sequence, last status read cycle, and array data read cycle. figure 19. toggle bit timings (during embedded algorithms) note: dq2 toggles only when read at an address within an erase-suspended sector. the system may use oe# or ce# to toggle dq2 and dq6. figure 20. dq2 vs. dq6 oe# ce# we# addresses t oeh t dh t aht t aso t oeph t oe valid data (first read) (second read) (stops toggling) t ceph t aht t as dq6 & dq14/ dq2 & dq10 valid data valid status valid status valid status ry/by# enter erase erase erase enter erase suspend program erase suspend read erase suspend read erase we# dq6 dq2 erase complete erase suspend suspend program resume embedded erasing
134 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics temporary sector unprotect notes: 1. not 100% tested. figure 21. temporary sector group unprotect timing diagram parameter all speed options jedec std description unit t vidr v id rise and fall time (see note) min 500 ns t rsp reset# setup time for temporary sector unprotect min 4 s reset# t vidr v id v ss , v il , or v ih v id v ss , v il , or v ih ce# we# ry/by# t vidr t rsp program or erase command sequence t rrb
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 135 preliminary ac characteristics note: for sector group protect, a6:a0 = 0xx0010. for sector group unprotect, a6:a0 = 1xx0010.n figure 22. sector group protect and unprotect timing diagram sector group protect: 150 s, sector group unprot ect: 15 ms 1 s reset# sa, a6, a3, a2, a1, a0 data ce# we# oe# 60h 60h 40h valid* valid* valid* status sector group protect or unprotect verify v id v ih
136 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics alternate ce# controlled erase and program operations-s29gl256m notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 10 11 t avav t wc write cycle time (note 1) min 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 ns effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns t poll program valid before status polling (note 5) max 4 s
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 137 preliminary ac characteristics alternate ce# controlled erase and program operations-s29gl128m notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 90 10 t avav t wc write cycle time (note 1) min 90 100 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 45 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 25 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 ns effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns t poll program valid before status polling (note 5) max 4 s
138 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics alternate ce# controlled erase and program operations-s29gl064m notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 90 10 11 t avav t wc write cycle time (note 1) min 90 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 ns effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns t poll program valid before status polling (note 5) max 4 s
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 139 preliminary ac characteristics alternate ce# controlled erase and program operations-s29gl032m notes: 1. not 100% tested. 2. see the ?erase and programming performance? section for more information. 3. for 1?16 words/1?32 bytes programmed. 4. effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. when using the program suspend/resume feature, if the suspend command is issued within t poll , t poll must be fully re-applied upon resuming the programming operation. if the suspend command is issued after t poll , t poll is not required again prior to reading the status bits upon resuming. parameter speed options unit jedec std. description 90 10 11 t avav t wc write cycle time (note 1) min 90 100 110 ns t avwl t as address setup time min 0 ns t elax t ah address hold time min 45 ns t dveh t ds data setup time min 35 ns t ehdx t dh data hold time min 0 ns t ghel t ghel read recovery time before write (oe# high to we# low) min 0 ns t wlel t ws we# setup time min 0 ns t ehwh t wh we# hold time min 0 ns t eleh t cp ce# pulse width min 35 ns t ehel t cph ce# pulse width high min 25 ns t whwh1 t whwh1 write buffer program operation (notes 2, 3) typ 240 ns effective write buffer program operation (notes 2, 4) per word typ 15 s accelerated effective write buffer program operation (notes 2, 4) per word typ 12.5 s t whwh2 t whwh2 sector erase operation (note 2) typ 0.5 sec t rh reset# high time before write min 50 ns t poll program valid before status polling (note 5) max 4 s
140 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary ac characteristics notes: 1. figure indicates last two bus cycles of an erase operation, or last cycle of a write-to-buffer operation followed by the program buffer to flash command. 2. pba = program buffer address, sa = sector address, pbd = program buffer data. 3. dq7# is the complement of the data written to the device. d out is the data written to the device. 4. illustration shows device in word mode. figure 23. alternate ce# controlled write (erase/program) operation timings t ghel t ws oe# ce# we# reset# t ds data t ah addresses t dh t cp dq7# d out t wc t as t cph pa data# polling pbd for program 55 for erase t rh t whwh1 or 2 t poll ry/by# t wh 29 for program buffer to flash 30 for sector erase 10 for chip erase pba for program 2aa for erase sa for program buffer to flash sa for sector erase 555 for chip erase t busy
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 141 preliminary erase and programming performance notes: 1. typical program and erase times assume the following conditions: 25 c; vcc = 3.0v; checkerboard data pattern. 2. under worst case conditions of 90 c; worst case v cc . 3. for 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. effective programming time (typ) is 1 5 s (per word), 7.5 s (per byte). 4. effective accelerated programming time (typ) is 12.5 s (per word), 6.3 s (per byte). 5. effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. in the pre-programming step of the embedded erase algorithm, all bits are programmed to 00h before erasure. 7. system-level overhead is the time required to execute the command sequence(s) for the program command. see tables 12 and 11 for further information on command definitions. 8. contact your local sales office for minimum cycling endurance values in specific applications and operating conditions. latchup characteristics note: includes all pins except v cc . test conditions: v cc = 3.0 v, one pin at a time. parameter typ (note 1) max (note 2) unit comments sector erase time 0.5 3.5 sec excludes 00h programming prior to erasure (note 6) chip erase time s29gl032m 32 64 sec s29gl064m 64 128 s29gl128m 128 256 s29gl256m 256 512 total write buffer program time (note 3) 240 s excludes system level overhead (note 7) total accelerated effective write buffer program time (note 4) 200 s chip program time s29gl032m 31.5 sec s29gl064m 63 s29gl128m 126 s29gl256m 252 description min max input voltage with respect to v ss on all pins except i/o pins (including a9, oe#, and reset#) ?1.0 v 12.5 v input voltage with respect to v ss on all i/o pins ?1.0 v v cc + 1.0 v v cc current ?100 ma +100 ma
142 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary tsop pin and bga package capacitance for package types ta, tf, ba, bf, fa, ff (refer to ordering information pages): for package types tb, tc, bb, bc (refer to ordering information pages): notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 6 7.5 pf bga 4.2 5.0 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 5.4 6.5 pf c in2 control pin capacitance v in = 0 tsop 7.5 9 pf bga 3.9 4.7 pf parameter symbol parameter description test setup typ max unit c in input capacitance v in = 0 tsop 8 10 pf bga 8 10 pf c out output capacitance v out = 0 tsop 8.5 12 pf bga 8.5 12 pf c in2 control pin capacitance v in = 0 tsop 8 10 pf bga 8 10 pf
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 143 preliminary physical dimensions ts040?40-pin standard/reverse thin small outline package (tsop) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b see detail b b b b b see detail a see detail a 2 reverse pin out (top view) 2 n +1 n n 1 4 3 a -a- -b- 5 9 e 5 d1 d 6 2 3 4 5 7 8 9 tsr 040 mo-142 (b) ec 40 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 9.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 10.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 10.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) not applicable. pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. 3324 \ 16-038.10a
144 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions tsr040?40-pin standard/reverse thin small outline package (tsop) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b see detail b b b b b see detail a see detail a 2 reverse pin out (top view) 2 n +1 n n 1 4 3 a -a- -b- 5 9 e 5 d1 d 6 2 3 4 5 7 8 9 tsr 040 mo-142 (b) ec 40 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 9.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 10.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 10.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) not applicable. pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. 3324 \ 16-038.10a
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 145 preliminary physical dimensions ts048?48-pin standard/reverse thin small outline package (tsop) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b see detail b b b b b see detail a see detail a 2 standard pin out (top view) 2 n +1 n n 1 4 2 a -a- -b- 5 9 e 5 d1 d 6 2 3 4 5 7 8 9 ts 048 mo-142 (b) ec 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 12.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) pin 1 identifier for standard pin out (die up). not applicable. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. 3325 \ 16-038.10a
146 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions tsr048?48-pin standard/reverse th in small outline package (tsop) -x- x = a or b e/2 detail b c l 0.25mm (0.0098") bsc 0? detail a r gage line parallel to seating plane b b1 (c) 7 6 c1 with plating base metal 7 c a-b s m 0.08mm (0.0031") section b-b e 0.10 c a2 plane seating c a1 see detail b see detail b b b b b see detail a see detail a 2 reverse pin out (top view) 2 n +1 n n 1 4 3 a -a- -b- 5 9 e 5 d1 d 6 2 3 4 5 7 8 9 tsr 048 mo-142 (b) ec 48 min 0.05 0.95 0.17 0.17 0.10 0.10 18.30 19.80 0.50 0? 0.08 11.90 0.50 basic max 0.15 1.20 0.27 0.16 0.21 5? 0.20 18.50 12.10 0.70 20.20 0.23 1.05 0.20 1.00 0.22 18.40 20.00 0.60 3? 12.00 nom symbol jedec package b1 a2 a1 a d l e e d1 b c1 c 0 r n 1 notes: controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982) not applicable. pin 1 identifier for reverse pin out (die down), ink or laser mark. to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15mm (.0059") per side. dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 (0.0031") total in excess of b dimension at max. material condition. minimum space between protrusion and an adjacent lead to be 0.07 (0.0028"). these dimensions apply to the flat section of the lead between 0.10mm (.0039") and 0.25mm (0.0098") from the lead tip. lead coplanarity shall be within 0.10mm (0.004") as measured from the seating plane. dimension "e" is measured at the centerline of the leads. 3326 \ 16-038.10a
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 147 preliminary physical dimensions ts056/tsr056?56-pin standard/reverse thin small outline package (tsop) notes: 1 controlling dimensions are in millimeters (mm). (dimensioning and tolerancing conforms to ansi y14.5m-1982.) 2 pin 1 identifier for standard pin out (die up). 3 pin 1 identifier for reverse pin out (die down), ink or laser mark. 4 to be determined at the seating plane -c- . the seating plane is defined as the plane of contact that is made when the package leads are allowed to rest freely on a flat horizontal surface. 5 dimensions d1 and e do not include mold protrusion. allowable mold protusion is 0.15 mm per side. 6 dimension b does not include dambar protusion. allowable dambar protusion shall be 0.08 mm total in excess of b dimension at max material condition. minimum space between protrusion and an adjacent lead to be 0.07 mm. 7 these dimesions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 8. lead coplanarity shall be within 0.10 mm as measured from the seating plane. 9 dimension "e" is measured at the centerline of the leads. 3160\38.10a mo-142 (b) ec ts/tsr 56 nom. --- --- 1.00 1.20 0.15 1.05 max. --- min. 0.95 0.20 0.23 0.17 0.22 0.27 0.17 --- 0.16 0.10 --- 0.21 0.10 20.00 20.20 19.90 14.00 14.10 13.90 0.60 0.70 0.50 3? 5? 0? --- 0.20 0.08 56 18.40 18.50 18.30 0.05 0.50 basic e r b1 jedec package symbol a a2 a1 d1 d c1 c b e l n o
148 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions laa064?64-ball fortified ball grid array (fbga)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 149 preliminary physical dimensions lac064?64-pin 18 x 12 mm package 3243 \ 16-038.12d package lac 064 jedec n/a 18.00 mm x 12.00 mm package symbol min nom max note a --- --- 1.40 profile height a1 0.40 --- --- standoff a2 0.60 --- --- body thickness d 18.00 bsc. body size e 12.00 bsc. body size d1 7.00 bsc. matrix footprint e1 7.00 bsc. matrix footprint md 8 matrix size d direction me 8 matrix size e direction n 64 ball count b 0.50 0.60 0.70 ball diameter ed 1.00 bsc. ball pitch - d direction ee 1.00 bsc. ball pitch - e direction sd / se 0.50 bsc. solder ball placement none depopulated solder balls notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jesd 95-1, spp-010 (except as noted). 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball row matrix size in the "d" direction. symbol "me" is the ball column matrix size in the "e" direction. n is the total number of solder balls. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row parallel to the d or e dimension, respectively, sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. not used. 9. "+" indicates the theoretical center of depopulated balls. bottom view side view top view 2x 2x c 0.20 c 0.20 6 7 7 a m m c c 0.10 0.25 b c 0.25 0.15 c a b c seating plane ed (ink or laser) corner a1 a2 d e 0.50 a1 corner id. 1.000.5 1.000.5 a a1 corner a1 nx b sd se ee e1 d1 1 2 3 4 5 6 7 8 a cb d fe g h
150 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions fba048?48-pin 6.15 x 8.15 mm package dwg rev af; 10/99
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 151 preliminary physical dimensions fbc048?48-pin 8 x 9 mm package dwg rev af; 10/99
152 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions fbe063?63-pin 12 x 11 mm package xfbe 063 dwg rev af; 10/99
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 153 preliminary physical dimensions fpt-48p-m19 ? .003 +.001 ? 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 ? 0.05 +.004 ? .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * *
154 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions fpt-56p-m01 18.400.10(.724.004) 20.000.20(.787.008) 14.000.10 m 0.10(.004) 0.100.05 (.004.002) 1 28 56 29 0.08(.003) (.551.004) (stand off) lead no. details of "a" part 0.600.15 (.024.006) 0?~8? .007.001 0.170.03 0.220.05 (.009.002) (mounting height) index "a" .043 ?.002 +.004 ?0.05 +0.10 1.10 0.50(.020) 0.25(.010) * 1 * 2
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 155 preliminary physical dimensions bga-48p-m20 8.00 0.20(.315 .008) 0.38 0.10(.015 .004) (stand off) (mounting height) 6.00 0.20 (.236 .008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48- ? 0.45 0.05 (48- ? .018 .002) m ? 0.08(.003) h g fed c ba 6 5 4 3 2 1 .043 ? .005 +.003 ? 0.13 +0.12 1.08 (index area)
156 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions bga-63p-m02 11.000.10(.433.004) .041 ?.004 +.006 ?0.10 +0.15 1.05 (mounting height) 1 2 3 4 5 6 7 8 a b c d e f g h 0.80(.031)typ (5.60(.220)) (5.60(.220)) index ball m 0.08(.003) 0.10(.004) index area 10.000.10 (.394.004) (7.20(.283)) j k (63-?0.18.002) 63-?0.450.05 ml (8.80(.346)) (4.00(.157)) 0.380.10 (.015.004) (stand off)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 157 preliminary physical dimensions bga-80p-m01 11.000.10(.433.004) 7.000.10 (.276.004) index area 0.380.10 (.015.004) (stand off) .043 ?.005 +.005 ?0.13 +0.12 1.08 (mounting height) a b c d e f g h j k l m 1 2 3 4 5 6 7 8 (80- ? .018.002) 80- ? 0.450.05 0.08(.003) m s a b b ref 0.80(.031) ref 0.40(.016) a s s 0.10(.004) (index area)
158 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary physical dimensions bga-80p-m02 13.00 0.10(.512 .004) 10.00 0.10 (.394 .004) index area 0.38 0.10 (.015 .004) (stand off) a b c d e f g h j k l m 1 2 3 4 5 6 7 8 (80- ? .018 .002) 80- ? 0.45 0.05 0.08(.003) m s a b b ref 0.80(.031) ref 0.40(.016) a s s 0.10(.004) (index area) .043 ?.005 +.005 ?0.13 +0.12 1.08 (mounting height)
january 29, 2004 s29glxxxma0 s29glxxxm mirrorbit tm flash family 159 preliminary revision summary revision a (january 29, 2004) initial release. trademarks and notice copyright ? 2004 fasl llc. all rights reserved. spansion, the spansion logo, mirrorbit, and combinations thereof are registered trademarks of fasl llc. expressflash is a trademark of fasl llc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .
160 s29glxxxm mirrorbit tm flash family s29glxxxma0 january 29, 2004 preliminary

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